When combining inductors, the baseline math mirrors resistors: inductance in series adds directly ($L_{total} = L_1 + L_2$), while inductance in parallel reciprocates ($1/L_{total} = 1/L_1 + 1/L_2$). However, this ideal math assumes zero mutual magnetic coupling between the components. In real-world power supply and RF filter design, combining inductors fundamentally alters the DC resistance (DCR), saturation current ($I_{sat}$), and thermal behavior of the network. Choosing between an inductance series parallel topology is rarely about just hitting a target microhenry ($\mu H$) value; it is about managing current limits, core losses, and failure cascades.
Topology Definitions and Node Behavior Matrix
To analyze these networks precisely, we define our nodes: Node A is the input terminal, Node B is the intermediate junction (in series) or the common bus (in parallel), and Node C is the output terminal. Below is the behavioral matrix detailing how real-world parameters shift when you configure physical inductors into these topologies.
| Parameter | Series Topology (A → L1 → B → L2 → C) | Parallel Topology (A → [L1 || L2] → C) | Impact if L1 Value Increases | Impact if L1 Fails Short |
|---|---|---|---|---|
| Total Inductance ($L_{eq}$) | $L_1 + L_2$ (Assuming $M=0$) | $(L_1 \times L_2) / (L_1 + L_2)$ | Series: $L_{eq}$ increases. Parallel: $L_{eq}$ increases slightly. |
Series: Drops to $L_2$. Parallel: Drops to 0 (Short Circuit). |
| Total DCR | $DCR_1 + DCR_2$ | $(DCR_1 \times DCR_2) / (DCR_1 + DCR_2)$ | No direct change (unless wire gauge changes). | Series: Drops to $DCR_2$. Parallel: Drops to near 0$\Omega$. |
| Saturation Current ($I_{sat}$) | Limited by the lowest $I_{sat}$ in the chain. | Sum of both $I_{sat}$ ratings (if DCR is perfectly matched). | No change to physical core limits. | Series: Limited by $L_2$. Parallel: Limited by $L_2$ (current shifts). |
| Failure Mode: L1 Opens | Circuit breaks entirely. $L_{eq}$ becomes infinite (open). | Network survives. $L_{eq}$ increases to equal $L_2$. | N/A | N/A |
Why Choose Series vs. Parallel Inductor Topologies
The decision to wire inductors in series or parallel usually stems from component availability or the need to optimize the DCR-to-current ratio. According to the Coilcraft Inductor Toolkit, understanding the physical limits of the magnetic core is critical before finalizing a topology.
When to Use Series Inductors
Choose a series topology when you need a high inductance value but only have smaller, standard-value inductors in stock, or when you need to increase the overall impedance of a filter without altering the current rating. In a series configuration, the total saturation current ($I_{sat}$) is strictly bottlenecked by the weakest component. If you place a 2A inductor in series with a 5A inductor, the network saturates at 2A. Furthermore, the DCR adds linearly, which increases $I^2R$ copper losses and reduces overall power supply efficiency.
When to Use Parallel Inductors
Parallel topologies are chosen to halve the DCR and double the current-handling capability. This is common in high-current, low-voltage buck converters where a single inductor with the required $\mu H$ and $I_{sat}$ would be physically massive or prohibitively expensive.
If you parallel two inductors with mismatched DCRs (e.g., 0.05$\Omega$ and 0.10$\Omega$), the lower-DCR inductor will hog the DC bias current. It will hit its $I_{sat}$ limit long before the second inductor does. Once the first core saturates, its inductance collapses, shifting the AC ripple current entirely to the second inductor, which then overheats and fails. Always parallel inductors from the exact same manufacturing batch, or intentionally add small ballast resistors to force current sharing.
Design Walkthrough: Sourcing a 44µH High-Current Choke
Suppose you are designing a SEPIC converter that requires roughly 44µH of inductance and must handle 2.5A of continuous DC current without saturating. You check your inventory and the TI Power Inductor Selection Guide for standard footprints. You have two options using the widely available Coilcraft DO3316P series:
- Option A (Series): Two DO3316P-223ML (22µH each).
Specs per part: 22µH, DCR = 0.070$\Omega$, $I_{sat}$ = 2.8A.
Network Result: 44µH total. DCR = 0.140$\Omega$. $I_{sat}$ = 2.8A. (Passes requirements) - Option B (Parallel): Two DO3316P-104ML (100µH each).
Specs per part: 100µH, DCR = 0.250$\Omega$, $I_{sat}$ = 1.2A.
Network Result: 50µH total. DCR = 0.125$\Omega$. $I_{sat}$ = 2.4A (assuming perfect sharing). (Fails $I_{sat}$ requirement)
In this scenario, the series configuration wins. While the parallel setup offers slightly lower DCR, its combined saturation current (2.4A) falls short of the 2.5A requirement, risking core saturation and catastrophic switching FET failure. The series setup easily handles 2.8A, though you must account for the extra 15m$\Omega$ of DCR in your thermal calculations.
Step-by-Step Breadboard Verification
Testing inductor networks on a solderless breadboard introduces significant parasitic variables. As noted in All About Circuits, ideal formulas assume isolated magnetic fields. Follow these steps to accurately verify your physical build:
- Configure the LCR Meter: Set your bench LCR meter (e.g., Keysight U1733C or DER EE DE-5000) to measure inductance (L) at 100 kHz with a 1Vrms test signal. This frequency approximates typical switching converter ripple.
- Perform Fixture Compensation: Short the test leads and run the SHORT compensation routine. Then, leave them open and run the OPEN compensation routine. This nulls out the lead inductance (typically 50-100nH) and parallel capacitance.
- Isolate the Components: Plug the inductors into the breadboard at least 1.5 inches apart. If placed side-by-side, their magnetic fields will couple, introducing mutual inductance ($M$) and invalidating the standard series/parallel formulas.
- Measure Individual Baselines: Probe Node A to Node B for L1, and Node B to Node C for L2. Record the exact values (e.g., 21.4µH and 21.8µH).
- Measure the Network: Probe Node A to Node C. Compare the measured $L_{eq}$ against your calculated sum. A variance greater than 5% indicates parasitic breadboard capacitance or unintended magnetic coupling.
The Hidden Trap: Mutual Coupling and Extreme Failures
The most common mistake hobbyists and junior engineers make when combining inductors is ignoring mutual inductance ($M$). If two inductors are placed physically close to one another, especially with their cores aligned, the magnetic flux from one links with the turns of the other.
When mutual coupling is present, the formulas change drastically:
- Series Aiding (fields reinforcing): $L_{total} = L_1 + L_2 + 2M$
- Series Opposing (fields canceling): $L_{total} = L_1 + L_2 - 2M$
If you place two 22µH inductors tightly side-by-side in series, you might measure 55µH (aiding) or 12µH (opposing) depending entirely on their physical orientation. To guarantee the standard $L_1 + L_2$ behavior, you must orient the inductors at 90-degree angles to one another or specify shielded-core components (like the Coilcraft MSS or Bourns SRP shielded series) which contain the flux within the component body.
Extreme Failure Cascades
When components fail, the topology dictates the collateral damage. In a parallel configuration, if one inductor's winding shorts out internally (a common failure mode under severe thermal stress), the entire network becomes a dead short across Node A and Node C. In a buck converter, this will instantly blow the high-side MOSFET and potentially destroy the load. Conversely, in a series configuration, an internal short in L1 simply removes it from the circuit; $L_{eq}$ drops to L2. The power supply will likely enter discontinuous conduction mode (DCM) or suffer from higher output ripple, but it usually survives long enough for the UVLO (Under-Voltage Lockout) circuitry to shut it down safely.
