The identity law in boolean algebra states that any boolean variable ORed with 0 or ANDed with 1 remains unchanged in its original logic state. In physical circuits and firmware, applying this law changes how you handle unused logic gate inputs, mask microcontroller registers, and optimize silicon area in FPGAs, directly impacting quiescent current draw, propagation delay, and overall system reliability.
When you are designing a digital system, ignoring the identity law doesn't just result in messy equations; it results in floating CMOS inputs that oscillate, destroy your power budget, and potentially latch up your ICs. This guide breaks down the exact mathematics, shows you where this law lives in real-world hardware, and provides a hard decision path for wiring physical logic chips.
The Core Formulas and a Worked Numeric Example
The identity law is defined by two primary equations. According to standard digital logic references like All About Circuits, these rules form the baseline for simplifying complex logic networks:
A + 0 = A (A variable ORed with FALSE remains unchanged)AND Identity:
A · 1 = A (A variable ANDed with TRUE remains unchanged)
To see how this works with real values, let's look at a common embedded systems task: bit-masking an 8-bit microcontroller GPIO port. Suppose you are reading a status register on an ESP32, and the current port state is 0b10110010 (decimal 178). You need to pass this value through a software filter that forces bit 0 to retain its current state, while you evaluate other bits elsewhere.
Worked Numeric Example:
- Initial Register State (A):
0b10110010 - Identity Mask (1):
0b11111111(Hex0xFF) - Operation (AND Identity):
A · 1 = A - Calculation:
0b10110010 AND 0b11111111 = 0b10110010
The output is exactly 0b10110010. The mask of all 1s acted as an identity element. Conversely, if you wanted to use the OR identity to preserve a value in a hardware multiplexer, you would OR the signal with 0b00000000. In both cases, the mathematical identity guarantees the signal passes through the logic gate without inversion or forcing to a static rail.
Where You Meet the Identity Law in Practice
You might think boolean algebra is just for passing college exams, but the identity law dictates physical wiring and firmware architecture on the bench every day.
1. Handling Unused Inputs on Physical ICs
If you are using a 74HC08 (Quad 2-input AND gate) but only need three of the gates, the fourth gate has two floating inputs. CMOS inputs have incredibly high impedance. If left floating, they act as antennas, picking up electromagnetic noise and causing the internal transistors to rapidly switch between high and low. This creates a massive spike in quiescent current (I_DD), overheating the chip. By applying the AND identity law (A · 1 = A), you tie the unused inputs to VCC (Logic 1). The gate now outputs whatever the other input is doing (or a static 1 if both are tied high), stabilizing the circuit and dropping the current draw back to microamps.
2. FPGA and CPLD Synthesis Optimization
When you write VHDL or Verilog and compile it for an FPGA, the synthesis tool (like Xilinx Vivado or Intel Quartus) uses the identity law to prune redundant Look-Up Tables (LUTs). If your code contains assign out = in_signal & 1'b1;, the synthesizer recognizes the AND identity, deletes the logic gate entirely, and routes in_signal directly to the output pin. This reduces propagation delay and saves silicon resources.
3. PLC Ladder Logic Troubleshooting
In industrial Programmable Logic Controllers, technicians often use the identity law to force a rung to evaluate without altering the core safety logic. By placing an "Always ON" (Logic 1) contact in series with a motor starter coil, the identity law ensures the coil's state is dictated entirely by the rest of the rung, allowing safe isolation of faults.
Identity Law vs. Null and Idempotent Laws
The most common mistake hobbyists and students make is confusing the identity law with the Null (Annulment) Law or the Idempotent Law. Mixing these up on a breadboard will result in short circuits or locked-up logic states. As outlined in Electronics Tutorials, keeping these distinct is critical for circuit simplification.
| Law Name | Formulas | What It Does | Physical Result if Confused with Identity |
|---|---|---|---|
| Identity | A + 0 = AA · 1 = A |
Preserves the variable's state. | N/A (This is the correct baseline). |
| Null (Annulment) | A + 1 = 1A · 0 = 0 |
Destroys the variable; forces a static output. | If you tie an AND gate input to GND (0) thinking it's the identity, you force the output permanently LOW, killing the signal. |
| Idempotent | A + A = AA · A = A |
Redundant duplication has no effect. | Wiring the same signal to both inputs of a gate works, but wastes a physical wire and increases capacitive load on the driving pin. |
Decision Path: Handling Unused Gate Inputs on Physical ICs
When you have leftover gates in a multi-gate IC package, you must terminate the inputs to prevent floating nodes. Use this decision tree to determine exactly how to wire them based on the gate type and your design constraints.
| Condition / Gate Type | Action Required | Termination Target |
|---|---|---|
| IF using an unused AND or NAND gate... | Apply AND Identity (A · 1 = A) |
Tie inputs to VCC (Logic 1). Use a 10kΩ pull-up resistor if VCC is noisy, or direct tie for clean 74HC rails. |
| IF using an unused OR or NOR gate... | Apply OR Identity (A + 0 = A) |
Tie inputs to GND (Logic 0). Direct tie to ground plane is acceptable. |
| IF using an unused Inverter (NOT gate)... | Force to a static state to prevent oscillation. | Tie input to GND (Output goes HIGH) or VCC (Output goes LOW). |
| IF you want to minimize board space and avoid tying off unused gates entirely... | Change the BOM to single-gate packages. | DEFAULT PICK: Use 74LVC1G08 (Single AND) or 74LVC1G32 (Single OR) in SOT-23-5 packages. |
The Final Recommendation: If you are designing a new PCB in 2026 and find yourself needing to tie off multiple unused inputs on a 74HC-series quad package, stop. The identity law proves you are carrying dead silicon. Switch your bill of materials to single-gate micro-packages like the Texas Instruments SN74LVC1G08. They cost roughly $0.15 in volume, draw nanoamps of quiescent current, and completely eliminate the need to route VCC/GND traces to unused identity pins, saving you routing space and preventing layout-induced noise.
Frequently Asked Questions
Can I just leave unused CMOS inputs floating if the output isn't connected?
No. Even if the output pin of the unused gate is not routed anywhere, the internal CMOS transistors will still oscillate if the inputs float. This oscillation draws significant dynamic current (often 10mA to 50mA per floating gate at high frequencies) and injects high-frequency noise into the shared VCC rail, which can cause brownouts or reset glitches in sensitive microcontrollers on the same board. Always apply the identity law and tie them to a rail.
Does the identity law apply to XOR gates?
Yes, but the identity constant is different. For an XOR gate, the identity law is A ⊕ 0 = A. To preserve a signal passing through an XOR gate, you must tie the unused input to Logic 0 (GND). If you tie it to Logic 1, it becomes an inverter (A ⊕ 1 = A'), which is the complement, not the identity.
Why do we use 10kΩ resistors to tie inputs to VCC instead of a direct wire?
A direct wire to VCC is perfectly fine for standard 74HC or 74LS logic in low-noise environments. However, in automotive or industrial environments with heavy inductive kickback, a 10kΩ pull-up resistor limits the current if a voltage spike accidentally couples into the input trace, protecting the internal ESD diodes of the IC. For modern 74LVC series running at 3.3V, direct ties are standard practice unless hot-swapping is involved.
