Understanding i Binary: Current Steering in DACs and Logic Circuits

In digital and mixed-signal electronics, "i binary" refers to the binary-weighted current steps (i, i/2, i/4) used to translate digital logic states into precise analog currents or high-speed differential signals. This architecture changes a real circuit by replacing slow, impedance-varying voltage dividers with constant-current steering, slashing signal settling times from microseconds down to nanoseconds. Beginners commonly confuse binary current steering (where a fixed reference current is merely routed to different output nodes) with binary voltage dividers (like R-2R resistor ladders, which suffer from RC time constant delays and varying output impedance).

The Mechanics of Binary Weighted Current (i)

To understand how an i binary system operates, look inside a current-steering Digital-to-Analog Converter (DAC). The system generates a master reference current ($I_{ref}$) and uses a network of matched transistors to create binary-scaled copies: $i$, $i/2$, $i/4$, $i/8$, and so on. When a digital bit is '1', its corresponding current is steered to the output node; when '0', it is steered to ground.

Think of it like routing highway traffic: instead of stopping and starting cars at a toll booth (voltage switching), the cars (electrons) are already moving at a constant speed, and you simply flip a diverter switch to send them down either the "output" lane or the "dump" lane.

Worked Numeric Example: 12-Bit DAC Calculation

Let's calculate the exact output current for a 12-bit binary-weighted DAC with a reference current of $I_{ref} = 40.96 \text{ mA}$.

• Full Scale Current ($I_{FS}$): 40.96 mA
• Resolution (LSB step, $i$): $40.96 \text{ mA} / 2^{12} = 40.96 \text{ mA} / 4096 = 10 \text{ \mu A}$

Suppose your microcontroller sends the binary word 100100000000 (Bits 11 and 8 are HIGH; all others LOW).

• Bit 11 weight: $2^{11} = 2048 \rightarrow 2048 \times 10 \text{ \mu A} = 20.48 \text{ mA}$
• Bit 8 weight: $2^8 = 256 \rightarrow 256 \times 10 \text{ \mu A} = 2.56 \text{ mA}$
• Total Output Current: $20.48 \text{ mA} + 2.56 \text{ mA} = 23.04 \text{ mA}$

Because the current sources are always on, the transition from 1000... to 1001... happens in nanoseconds, limited only by the switching speed of the MOSFETs, not by the charging of a massive capacitor.

Where You Meet This in Practice

You will rarely build a discrete i binary ladder from scratch using individual BJTs or MOSFETs; the transistor matching required for 12-bit accuracy is impossible on a standard FR4 workbench. Instead, you will encounter this topology inside specific integrated circuits and high-speed interfaces.

1. High-Speed Current-Steering DACs

RF transmitters, arbitrary waveform generators (AWGs), and software-defined radios (SDRs) rely on i binary DACs. Parts like the AD9144 use current steering to achieve sample rates in the gigasamples-per-second (GSPS) range. Voltage-mode DACs simply cannot settle fast enough for these applications.

2. Current Mode Logic (CML)

In high-speed serial links like PCIe, USB 3.0, and 10G Ethernet, the physical layer uses Current Mode Logic. CML relies on a constant binary current source (typically 4 mA to 8 mA) that is steered between two differential output lines. The voltage swing is created by passing this steered current through 50-ohm termination resistors, resulting in a tight, fast differential signal that is highly immune to common-mode noise.

3. Industrial 4-20mA Control Loops

While a 4-20mA loop is an analog standard, modern loop transmitters generate this current using an internal i binary DAC. The microcontroller calculates the required sensor value, outputs a binary word to an internal current-steering DAC, and uses an op-amp feedback loop to force the exact current down the twisted pair cable.

Decision Path: Selecting Your Binary Current Architecture

Choosing the right implementation depends entirely on your speed, resolution, and interface requirements. Use the decision matrix below to terminate your search with a concrete part number.

Layout Rules and Failure Modes

When designing the PCB layout for an IC that utilizes an i binary output stage (like the DAC0808 or high-speed CML drivers), ignoring physical layout will destroy the theoretical performance of the silicon.

Compliance Voltage Violations

The current-steering transistors require a minimum voltage drop across their collector/drain to remain in the active (constant current) region. This is the compliance voltage. If your load resistance is too high, the output voltage will rise, pushing the steering transistors into saturation. Result: Severe non-linearity and a collapsed full-scale output. Always calculate $V_{drop} = I_{out} \times R_{load}$ and ensure it stays within the datasheet's compliance window (typically 0.5V to 1.2V for 5V parts).

Charge Injection and Glitch Impulse

When the MOSFET switches steer the binary current from the dummy node to the output node, the parasitic gate-to-drain capacitance injects a tiny packet of charge into the output line. This causes a momentary voltage spike known as a glitch. In audio or precision DC applications, this glitch is filtered out by an external RC network or op-amp bandwidth limit. In high-speed RF, it manifests as spurious harmonic distortion (SFDR degradation).

CML Impedance Matching

If you are routing CML (binary current logic) on a PCB, the traces must be routed as 50-ohm single-ended (100-ohm differential) controlled impedance lines. Because CML relies on $V = I \times R$, any deviation in trace impedance directly alters the logic voltage swing, potentially causing the receiver to misinterpret a binary '1' as a '0'.

FAQ: Binary Current Nuances