To convert a 400V DC bus to a 12V DC output using a half bridge converter with a 10:1 step-down transformer ($N_p:N_s$), the required duty cycle ($D$) is exactly 60% (0.60). The primary winding experiences a peak voltage swing of 200V ($V_{in}/2$), and each primary-side MOSFET must block the full 400V bus. This calculation assumes Continuous Conduction Mode (CCM), ideal switches, and zero dead-time.

The Core Conversion Formula

In a half-bridge topology, the primary winding is connected between the midpoint of a split capacitor bank and the midpoint of two switching MOSFETs. Because the capacitors divide the input voltage in half, the maximum voltage applied to the transformer primary during a switch ON-state is only $V_{in}/2$. This is the defining advantage over a full-bridge, which applies the full $V_{in}$ to the primary.

The DC-DC voltage conversion ratio for a half-bridge in CCM is:

V_out = (V_in / 2) × D × (N_s / N_p)

Substituting our 400V to 12V query values:

  • 12V = (400V / 2) × D × (1 / 10)
  • 12V = 200V × D × 0.1
  • 12V = 20V × D
  • D = 12 / 20 = 0.60 (60%)

Neighboring Values: ±20% Input Variance

Power grids and rectified buses are rarely perfect. If your 400V nominal bus sags or surges, the control loop must adjust the duty cycle to maintain 12V at the secondary. Here is how the required duty cycle shifts across a ±20% input range, assuming the 10:1 transformer remains fixed:

Input Voltage ($V_{in}$)VarianceRequired Duty Cycle ($D$)Primary Peak Voltage
320V-20%0.750 (75.0%)160V
360V-10%0.667 (66.7%)180V
400VNominal0.600 (60.0%)200V
440V+10%0.545 (54.5%)220V
480V+20%0.500 (50.0%)240V

Note: Most modern PWM controllers (like the TI UCC28780 family) cap maximum duty cycle around 70-75% per leg to prevent transformer saturation. A 320V sag pushes you right to that limit.

The Core Conversion Formula and Fixed Assumptions

The 60% duty cycle calculated above is a theoretical ideal. In physical hardware, three fixed assumptions dictate whether your converter actually outputs 12V or sags to 10.5V under load:

  1. Continuous Conduction Mode (CCM): The formula only holds true if the output inductor current never falls to zero during the switching cycle. If the load drops and the converter enters Discontinuous Conduction Mode (DCM), the output voltage becomes load-dependent, and the simple turns-ratio formula breaks down entirely.
  2. Zero Dead-Time: To prevent shoot-through (both MOSFETs conducting simultaneously and shorting the bus), a dead-time (typically 100ns to 200ns) must be inserted between switch transitions. At a 2026-standard switching frequency of 500kHz (using GaN FETs), a 200ns dead-time consumes 10% of the switching period. This effectively clamps your maximum usable duty cycle and introduces a voltage drop that the feedback loop must compensate for by slightly widening the pulse.
  3. Ideal Transformer (No Leakage Inductance): Real transformers have leakage inductance. When the secondary rectifiers commutate, this leakage inductance causes a 'duty cycle loss' at the secondary side. The primary voltage might be ON for 60% of the cycle, but the secondary might only see 56% due to the time it takes for the leakage current to ramp up and down.

Input Voltage Shifts: 120V vs 230V vs 3-Phase Buses

A common mistake in power supply design is assuming a single transformer turns ratio will work across global AC mains inputs. Because the half-bridge primary only sees half the bus voltage, it is highly sensitive to low-line conditions. Below is a data-dense breakdown of how the conversion shifts based on the rectified AC source, targeting the same 12V output with our 10:1 transformer.

AC Mains SourceRectified DC Bus ($V_{in}$)Primary Peak ($V_{in}/2$)Required Duty Cycle (10:1 TX)Recommended 2026 FET Tech
120VAC (1-Phase)~170V DC85V1.41 (Invalid)N/A (Requires 5:1 TX)
230VAC (1-Phase)~325V DC162.5V0.738 (73.8%)600V Si Superjunction
277VAC (1-Phase)~392V DC196V0.612 (61.2%)650V GaN (e.g., CoolGaN)
400VAC (3-Phase)~565V DC282.5V0.424 (42.4%)900V SiC MOSFET

The 120VAC Trap: Notice the 120VAC row. A rectified 120VAC line yields roughly 170V DC. The half-bridge applies only 85V to the primary. To get 12V out with a 10:1 transformer, the math demands a duty cycle of 1.41 (141%). Since duty cycle cannot exceed 1.0 (and practically caps at ~0.75), a 10:1 transformer is physically incapable of regulating 12V from a 120VAC line in a half-bridge topology. You must either drop the turns ratio to 4:1 or switch to a forward/flyback topology for low-line inputs. For a deeper look at topology selection, refer to All About Circuits' guide on isolated DC-DC converters.

When the Voltage Conversion Ratio Becomes Meaningless

While the $V_{out} = (V_{in}/2) × D × (N_s/N_p)$ formula is the bedrock of initial magnetics design, there are three specific scenarios where relying on this unit conversion will lead to a failed prototype:

1. Severe Light-Load Conditions (DCM)

If your 600W half-bridge converter drops to a 10W standby load, the output inductor current will hit zero before the next switching cycle begins. In this Discontinuous Conduction Mode, the output voltage is no longer fixed by the duty cycle and turns ratio alone; it becomes a function of the load current, inductance value, and switching frequency. The control loop will drastically reduce the duty cycle (often down to 10-15%) to maintain 12V, rendering the nominal CCM calculation meaningless.

2. High Leakage Inductance at High Currents

At 50A output current (600W), secondary-side commutation is violent. If your transformer is poorly wound (e.g., primary and secondary windings are not interleaved), leakage inductance will cause significant voltage ringing and duty-cycle loss. The primary MOSFETs might be driven at 60% duty cycle, but the secondary rectifiers might only conduct for 52% of the cycle due to the time required to transfer energy out of the leakage field. You will measure 10.4V at the output instead of 12V, forcing the controller to hit its maximum duty cycle limit and lose regulation.

3. Capacitor Imbalance

The half-bridge relies on the split input capacitor bank ($C_1$ and $C_2$) to provide exactly $V_{in}/2$. If these capacitors have mismatched Equivalent Series Resistance (ESR) or capacitance values, or if the transformer primary draws a net DC current due to slight asymmetries in the gate drive signals, the midpoint voltage will drift. If the midpoint drifts to $0.6 × V_{in}$, your primary peak voltage increases, pushing your output voltage out of regulation and potentially saturating the transformer core on one half of the switching cycle.

Design Rule of Thumb for 2026: When designing the split capacitor bank for a 400V bus, do not just match the capacitance. Use 1% tolerance film capacitors or tightly matched electrolytic caps with balancing resistors, and ensure your gate driver (like a TI UCC21530) has strictly matched propagation delays (typically < 2ns mismatch) to prevent flux walking and midpoint drift.