A half adder is a fundamental combinational logic circuit that adds two single-bit binary inputs to produce a Sum bit and a Carry-out bit. It achieves this using exactly two logic gates: an XOR gate to generate the Sum, and an AND gate to generate the Carry. If you are designing a basic Arithmetic Logic Unit (ALU) or debugging digital logic on a bench, understanding the half adder is the mandatory starting point for all binary math.

Unlike sequential logic circuits that rely on clock edges and memory, a half adder is purely combinational. The outputs change strictly as a function of the current inputs. Below, we break down the exact logic, the real-world timing constraints of physical silicon, and where this circuit actually lives in modern hardware.

The Half Adder Truth Table and Gate Logic

To understand the circuit, you must look at the binary math it performs. When adding two single bits (A and B), the lowest possible sum is 0 (0+0) and the highest is 2 (1+1). Because a single bit can only represent 0 or 1, a sum of 2 requires two bits to express: a Sum of 0 and a Carry of 1 (binary 10).

Table 1: Half Adder Truth Table and Gate Implementation
Input A Input B Sum Output Carry Output Boolean Expression Physical Gate Used
0 0 0 0 Sum = 0 ⊕ 0; Carry = 0 · 0 XOR / AND
0 1 1 0 Sum = 0 ⊕ 1; Carry = 0 · 1 XOR / AND
1 0 1 0 Sum = 1 ⊕ 0; Carry = 1 · 0 XOR / AND
1 1 0 1 Sum = 1 ⊕ 1; Carry = 1 · 1 XOR / AND

The Sum output is high only when the inputs are different, which is the exact definition of an Exclusive-OR (XOR) operation. The Carry output is high only when both inputs are high, which maps perfectly to a standard AND gate. For physical implementation on a breadboard or PCB, this means you only need two gates. You can pull these from standard 74-series logic ICs, such as the SN74HC86 (Quad 2-Input XOR) and the SN74HC08 (Quad 2-Input AND).

Worked Numeric Example: Propagation Delay in Real ICs

In textbook theory, logic gates switch instantly. On a real workbench, they do not. Every logic gate introduces a propagation delay ($t_{pd}$), which is the time it takes for a change at the input to reflect at the output. This delay fundamentally changes how you design clocked digital systems.

Let us calculate the timing for a half adder built from Texas Instruments 74HC-series CMOS chips operating at $V_{CC} = 5V$ with a standard $50pF$ capacitive load:

  • AND Gate (74HC08): Typical $t_{pd}$ = 10 ns
  • XOR Gate (74HC86): Typical $t_{pd}$ = 14 ns

If inputs A and B transition simultaneously from 00 to 11, the Carry output (driven by the AND gate) will stabilize at logic HIGH in 10 ns. However, the Sum output (driven by the XOR gate) will not stabilize to logic LOW until 14 ns have passed.

What this changes in a real circuit: The 14 ns delay of the XOR gate becomes the critical path for the entire half adder. If you are using this half adder inside a synchronous system, your clock period must be longer than 14 ns to avoid sampling the Sum bit before it settles. This limits your maximum safe clock frequency to roughly $71.4 ext{ MHz}$ ($1 / 14 ext{ns}$). If you attempt to clock the system at 100 MHz (a 10 ns period), the flip-flop capturing the Sum output will enter a metastable state, resulting in catastrophic arithmetic errors downstream.

When designing high-speed adders, engineers must account for these nanosecond-level mismatches, often swapping standard CMOS for Advanced Schottky TTL (like the 74AS series) or moving the design entirely into an FPGA where routing delays are mathematically modeled by the place-and-route tool.

Where You Meet Half Adders in Practice

While you will rarely see a discrete half adder on a modern motherboard, the logic structure is embedded deeply inside larger silicon architectures. Here is where this specific gate combination actually does work:

1. The Least Significant Bit (LSB) of an ALU

When a microcontroller adds two 32-bit numbers, it uses a chain of adders. The very first stage—adding bit 0 of operand A to bit 0 of operand B—has no previous carry to worry about. Therefore, the LSB position in a ripple-carry or carry-lookahead adder is almost always implemented as a half adder to save silicon area and reduce power consumption.

2. Parity Generators and ECC Memory

Error-Correcting Code (ECC) RAM and UART serial communication rely on parity bits to detect data corruption. Parity is generated by XORing a string of data bits together. Because the XOR half of a half adder performs exactly this function, large parity trees in memory controllers are essentially cascaded half adders where the AND (Carry) gates are simply omitted from the silicon layout.

3. FPGA Look-Up Tables (LUTs)

In modern FPGAs (like the Xilinx Artix-7 or Intel Cyclone series), logic is not built from discrete AND/XOR gates. Instead, it uses 4-input or 6-input Look-Up Tables (LUTs). A 6-input LUT can easily map the entire half adder truth table into its SRAM configuration, and still have enough input capacity to simultaneously evaluate a secondary logic function, making half adders virtually 'free' in terms of FPGA resource utilization.

Half Adder vs. Full Adder: The Common Confusion

The most common mistake digital design students make is attempting to cascade half adders to add multi-bit numbers. This fails because a half adder lacks a Carry-In ($C_{in}$) pin. It cannot accept the overflow from a previous mathematical stage. This is the exact distinction between a half adder and a full adder.

Table 2: Half Adder vs. Full Adder Specifications
Feature Half Adder Full Adder
Total Inputs 2 (A, B) 3 (A, B, $C_{in}$)
Total Outputs 2 (Sum, $C_{out}$) 2 (Sum, $C_{out}$)
Core Gates Required 1 XOR, 1 AND 2 XOR, 2 AND, 1 OR
Cascadability No (Only usable for LSB) Yes (Can chain infinitely)
Typical 74-Series IC Custom wiring of 74HC86 + 74HC08 74HC283 (Contains four full adders)

A full adder is essentially constructed by combining two half adders and an OR gate. The first half adder adds A and B. The second half adder adds the resulting Sum to the $C_{in}$ bit. The OR gate monitors the Carry outputs of both half adders; if either generates a carry, the final $C_{out}$ goes high.

Frequently Asked Questions

Can I build a half adder using only NAND gates?

Yes. Because the NAND gate is a 'universal gate,' you can construct any boolean function with it. Building a half adder requires exactly five NAND gates: two configured to act as the XOR function for the Sum, and a separate configuration to derive the AND function for the Carry. This is a standard exercise in MIT's Computation Structures coursework to prove boolean completeness.

Why is it called a 'half' adder?

It is called a half adder because it only performs 'half' the work required for multi-bit binary addition. It can add two bits, but it cannot accept a carry from a lower-order bit. To perform complete, cascaded arithmetic, you must use a full adder, which handles the current bits plus the carry from the previous stage.

What happens if I leave one input of a half adder floating?

In physical CMOS logic (like the 74HC series), a floating input acts as an antenna, picking up electromagnetic noise and causing the gate to oscillate wildly between HIGH and LOW. This will result in a rapidly toggling Sum and Carry output, excessive current draw, and potential thermal damage to the IC. Always tie unused logic inputs to either $V_{CC}$ or GND using a 10kΩ pull-up or pull-down resistor.