When you are reading a schematic or reverse-engineering a PCB, the shapes on the page dictate how signals flow. However, a shape that means 'AND' in an American datasheet might look completely different on a European industrial schematic. Understanding gate logic symbols requires knowing not just the basic shapes, but the regional standard the designer used. Below is the definitive reference for mapping these symbols to physical silicon, boolean math, and real-world bench behavior.

The Master Gate Logic Symbols Reference Chart

The table below maps the seven fundamental logic gates across the two dominant modern standards (ANSI/IEEE and IEC), along with their boolean expressions, truth tables, and the most common physical IC part numbers you will find in a parts bin. Use this as your primary lookup when tracing signals on a breadboard or schematic.

Gate Type ANSI/IEEE Shape IEC 60617 Box Boolean Expression Truth Table (A,B → Y) Common IC (DIP/SOIC)
AND D-shaped (flat back, curved front) Rectangle with & A · B 1,1 → 1 (else 0) 74HC08 / CD4081
OR Curved back, pointed front Rectangle with ≥1 A + B 0,0 → 0 (else 1) 74HC32 / CD4071
NOT (Inverter) Triangle with output bubble Rectangle with 1 and bubble A' 1 → 0, 0 → 1 74HC04 / CD4069
NAND D-shape with output bubble Rectangle with & and bubble (A · B)' 1,1 → 0 (else 1) 74HC00 / CD4011
NOR Curved back, pointed, with bubble Rectangle with ≥1 and bubble (A + B)' 0,0 → 1 (else 0) 74HC02 / CD4001
XOR D-shape with double curved back line Rectangle with =1 A ⊕ B 0,1 → 1; 1,0 → 1 74HC86 / CD4030
XNOR XOR shape with output bubble Rectangle with =1 and bubble (A ⊕ B)' 0,0 → 1; 1,1 → 1 74HC266 / CD4077

Note: The 'bubble' (a small circle on the input or output line) universally denotes logical inversion across both ANSI and IEC standards. For a deeper dive into how these gates are constructed internally using MOSFETs, refer to the All About Circuits digital logic chapter.

ANSI vs. IEC vs. DIN: Which Standard Applies to You?

If you have ever stared at a schematic full of rectangular boxes with numbers inside and wondered where the 'D-shapes' went, you are looking at an IEC standard schematic. The region and industry dictate which gate logic symbols the engineer will use.

ANSI/IEEE Std 91 (The 'Distinctive Shape' Standard)

Dominant in the United States, North America, and most hobbyist/educational contexts. This standard uses distinctive shapes for each gate. The physical shape of the symbol tells you the function at a glance without reading any text. This is the default in almost all Arduino/ESP32 schematics, hobbyist breadboard diagrams, and US-based university coursework.

IEC 60617 (The 'Rectangular Box' Standard)

Mandated in Europe, the UK, and most international industrial automation (PLC) schematics. IEC uses a uniform rectangular box for every gate. The function is defined by the text inside the box (& for AND, ≥1 for OR, =1 for XOR). While it looks like a mess of identical boxes to an ANSI-trained eye, IEC scales much better for complex, multi-input gates (like an 8-input AND gate) and programmable logic arrays where drawing distinctive shapes becomes visually chaotic.

DIN 40700 (The Legacy Standard)

You will rarely see this in new designs, but if you are repairing vintage European audio gear, old Siemens industrial controllers, or 1980s telecommunications racks, you will encounter DIN. DIN used a mix of rectangles and semi-circles that look like a hybrid of ANSI and IEC. Safe interpretation: If the schematic is dated before 1990 and originates from Germany or Eastern Europe, assume DIN. Cross-reference the part numbers printed on the physical PCB rather than trusting the symbol shapes.

Warning: Mixing Logic Families on the Bench
When probing physical ICs that represent these symbols, never mix 74LS (TTL) and 4000-series (CMOS) without checking voltage thresholds. A 74LS08 AND gate expects a logic HIGH above 2.0V, while a CD4081 CMOS gate expects a HIGH near VCC (e.g., 9V). Driving a 9V CMOS output directly into a 5V TTL input will destroy the TTL silicon. Always use a level shifter or a voltage divider when crossing logic families.

The 'Rows People Get Wrong' and Faded Silkscreen Survival

Even experienced engineers misread specific gate logic symbols under poor lighting or when dealing with degraded PCBs. Here are the most common pitfalls and how to recover when the board markings are gone.

Rows People Get Wrong

  • XOR vs. OR: The XOR symbol in ANSI is identical to the OR symbol, except for a second, disconnected curved line on the input side. On poorly printed schematics or low-resolution PDFs, that second line blends into the input wires, causing designers to miswire parity-check circuits.
  • The Inversion Bubble Placement: A bubble on the output means the gate's final result is inverted (e.g., NAND). A bubble on the input means the gate triggers on a logic LOW (Active-Low). In modern memory and microcontroller schematics, you will frequently see AND gates with bubbles on the inputs. This isn't a NAND gate; it is an Active-Low enable circuit (often labeled /CE or /CS).
  • XNOR vs. XOR: Because XNOR is just XOR with a bubble, it is often missed in dense logic arrays. Remember that XNOR acts as a digital comparator: the output is HIGH only when both inputs match (both 0 or both 1).

Faded Silkscreen Survival: Identifying a Mystery Gate

Suppose you are salvaging components from a dead motherboard and find an unmarked SOIC-14 chip. The silkscreen is burned off. How do you safely identify which gate logic symbols it contains without a datasheet?

  1. Locate Power and Ground: For 95% of standard 14-pin logic ICs (like the 74HC or CD40 series), Pin 7 is Ground (GND) and Pin 14 is VCC. Pin 1 is always to the left of the notch/dot when the chip is oriented upright.
  2. Power it Safely: Place the chip on a breadboard. Apply 3.3V or 5V to Pin 14 and GND to Pin 7. Do not exceed 5.5V unless you have verified it is a 4000-series CMOS chip (which can take up to 15V).
  3. Map the Truth Table: Pick a gate section (e.g., Pins 1 & 2 are inputs, Pin 3 is output). Use 10kΩ pull-up/pull-down resistors to tie the inputs to VCC (Logic 1) or GND (Logic 0). Measure the output with a multimeter.
  4. Match the Table: If 1,1 yields 0, and all other combinations yield 1, you are holding a NAND gate. Cross-reference your findings with the master table above to identify the exact IC family.

Bench Verification: Matching Symbols to Physical ICs

Symbols on a page are theoretical; the silicon on your bench is physical. When translating gate logic symbols into a parts list, you must select the correct logic family based on your system's voltage and speed requirements. For comprehensive datasheet specifications, you can reference the Texas Instruments SN74HC08 product page or similar manufacturer portals.

Logic Family Prefix Example VCC Range Propagation Delay Best Application
74HC (High-Speed CMOS) 74HC08 2.0V to 6.0V ~8ns @ 5V General purpose, battery-powered 3.3V/5V systems
74LS (Low-Power Schottky TTL) 74LS08 4.75V to 5.25V ~15ns Legacy 5V repairs, strict TTL threshold needs
74LVC (Low-Voltage CMOS) 74LVC1G08 1.65V to 5.5V ~5ns Modern 1.8V/3.3V microcontrollers (ESP32, STM32)
CD4000 (Standard CMOS) CD4081 3.0V to 15.0V ~50ns @ 5V High-voltage analog/digital mixing, 9V/12V systems

When wiring these physical ICs, remember that unused inputs on CMOS gates (HC, LVC, CD40) must never be left floating. A floating input acts as an antenna, picking up ambient RF noise and causing the internal MOSFETs to oscillate rapidly. This leads to excessive current draw, thermal runaway, and eventually a melted chip. Always tie unused inputs to VCC or GND, or use a modern single-gate IC (like the 74LVC1G series in a 5-pin SOT-23 package) to eliminate wasted gates entirely.

For further reading on how these physical gates are combined to build adders, multiplexers, and flip-flops, the Electronics Tutorials logic gate guide provides excellent step-by-step circuit breakdowns.