The voltage gain of a standard non-inverting op-amp circuit is calculated as Av = 1 + (Rf / Rg). If you need a precise gain of 11, use a 10kΩ feedback resistor (Rf) and a 1kΩ ground resistor (Rg). While the math is straightforward, real-world implementation requires managing input impedance, decoupling, and the Gain-Bandwidth Product (GBWP). Below is a complete design walkthrough, failure-mode analysis, and breadboard testing protocol for the non-inverting topology.
The Non-Inverting Topology: Nodes, Labels, and the Gain Formula
In the non-inverting configuration, the input signal is applied to the high-impedance non-inverting node, while negative feedback is routed to the inverting node. Here are the standard node labels for this topology:
- Vin: The input signal, connected to the non-inverting input (V+ or Pin 3 on a standard dual op-amp).
- Vout: The amplified output signal (Pin 1 or Pin 7).
- V-: The inverting input (Pin 2 or Pin 6), acting as the summing junction.
- Rf: The feedback resistor, connected between Vout and V-.
- Rg: The ground resistor, connected between V- and circuit common (GND).
Because of the op-amp's high open-loop gain, the negative feedback forces the voltage at V- to equal the voltage at V+ (the "virtual short" principle). The current flowing through Rg must equal the current flowing through Rf, yielding the gain formula: Av = 1 + (Rf / Rg).
The inverting amplifier has an input impedance equal to its input resistor (often 1kΩ to 10kΩ), which will heavily load high-impedance sources like piezo sensors or passive guitar pickups. The non-inverting topology presents the op-amp's native common-mode input impedance to the source. For a JFET-input op-amp like the TL072, this is typically 1012 Ω. It buffers the source while amplifying the signal, making it the default choice for sensor front-ends and audio preamps.
Design Walkthrough: Dialing in a Gain of 11
Let's design a low-noise AC amplifier with a gain of 11. We will use the Texas Instruments TL072CP, a low-noise JFET-input dual op-amp, powered by a dual ±12V DC supply to allow for symmetrical AC signal swings without DC biasing networks.
Component Selection
- U1: TL072CP (8-pin DIP).
- Rf: 10.0 kΩ, 1% tolerance metal film (e.g., Yageo MFR-25 series). Metal film minimizes thermal noise compared to carbon composition.
- Rg: 1.00 kΩ, 1% tolerance metal film. (Gain = 1 + 10k/1k = 11).
- Cdec: Two 100 nF X7R MLCC capacitors for power rail decoupling.
With a 100 mVpp sine wave at Vin, the circuit will output a 1.1 Vpp sine wave at Vout, perfectly in phase with the input. According to Analog Devices' op-amp fundamentals guide, maintaining 1% resistor tolerance ensures your closed-loop gain deviates by no more than ~2% from the ideal calculation, accounting for standard series resistance combinations.
Element Behavior and Extreme Failure Modes
Understanding how the circuit behaves when components drift or fail is critical for bench troubleshooting. The table below outlines the mathematical behavior when elements are changed, followed by the hard failure modes.
| Element Changed | Direction of Change | Effect on Circuit Gain (Av) | Secondary Effect |
|---|---|---|---|
| Rf (Feedback) | Increases | Gain Increases | Bandwidth decreases (due to constant GBWP); noise floor rises. |
| Rf (Feedback) | Decreases | Gain Decreases | Bandwidth increases; op-amp output stage sources more current. |
| Rg (Ground) | Increases | Gain Decreases | Approaches unity gain (buffer) as Rg → ∞. |
| Rg (Ground) | Decreases | Gain Increases | Bandwidth decreases; V- node draws more current from Vout. |
What Breaks at the Extremes (Open and Short Failures)
When debugging a dead board, you must know what the op-amp does when a passive component catastrophically fails. As detailed in All About Circuits' analysis of op-amp limits, removing the feedback path destroys the virtual short.
- Rf Opens: The feedback loop is broken. The op-amp reverts to its massive open-loop gain (typically 100,000+). Microvolt noise or input offset voltage at the pins is amplified infinitely, causing the output to slam into the positive or negative supply rail (saturation). Symptom: Vout is stuck at +11V or -11V DC.
- Rg Opens: Rg becomes infinite. The term (Rf / Rg) becomes zero. The gain drops to exactly 1. The circuit inadvertently becomes a unity-gain voltage follower (buffer). Symptom: Vout perfectly mirrors Vin with no amplification.
- Rf Shorts: Rf becomes 0Ω. Vout is directly hardwired to V-. The gain becomes 1 (unity buffer). The op-amp will safely drive the output to match V+, while Rg simply acts as a passive load to ground drawing Vin / Rg current. Symptom: Gain = 1, slight increase in op-amp thermal dissipation.
- Rg Shorts: V- is hard-tied to ground (0V). The feedback network can no longer pull V- up to match V+. The op-amp output will rail positive in a futile attempt to achieve equilibrium. Symptom: Vout slammed to positive rail; Rf may overheat if Vout current exceeds limits.
Step-by-Step Breadboard Testing Procedure
Do not apply power until the feedback network is verified. Follow this sequence to avoid latching up the IC or oscillating the output.
- Seat the IC: Place the TL072CP across the breadboard center trench. Pin 1 (Output A) and Pin 4 (V-) should be on the left side; Pin 5 (V+) and Pin 8 (VCC+) on the right.
- Wire Power and Decoupling: Connect +12V to Pin 8 and -12V to Pin 4. Place a 100 nF MLCC capacitor directly across Pin 8 and ground, and another across Pin 4 and ground. Never skip decoupling; high-gain op-amps will oscillate at RF frequencies without it.
- Wire the Feedback Network: Insert the 10kΩ Rf from Pin 1 (Vout) to Pin 2 (V-). Insert the 1kΩ Rg from Pin 2 (V-) to the ground rail.
- Connect the Input: Wire your signal generator output to Pin 3 (V+). Ensure the signal generator ground is tied to the breadboard ground.
- Power On and Verify DC Offset: Turn on the power supply. With no AC signal applied (or generator set to 0V), measure Pin 1 with a multimeter. It should read between -2mV and +2mV (the TL072's typical input offset voltage). If it reads ±11V, you have a wiring fault or an open feedback loop.
- Apply AC and Measure: Set the generator to a 1 kHz sine wave at 100 mVpp. Probe Pin 1 with an oscilloscope. You should see a clean 1.1 Vpp sine wave. If the waveform looks like a triangle, you have exceeded the op-amp's slew rate (0.5 V/µs for the TL072); reduce the input amplitude or frequency.
Frequently Asked Questions
How does the gain-bandwidth product limit the gain of an op amp circuit?
The Gain-Bandwidth Product (GBWP) is a constant for a given op-amp. The TL072 has a typical GBWP of 3 MHz. If your closed-loop gain is 11, your maximum usable bandwidth (the -3dB point) is 3,000,000 / 11 = 272 kHz. If you attempt to amplify a 500 kHz signal with this circuit, the actual gain of the op amp circuit will roll off significantly below your calculated 11. For high-frequency, high-gain applications, you must select an op-amp with a higher GBWP, such as the OPA1612 (40 MHz GBWP).
Why is my measured gain of the op amp circuit lower than the calculated value?
If your DC and low-frequency AC measurements match the formula, but high-frequency gain drops, you are hitting the GBWP limit or parasitic capacitance roll-off. However, if your gain is low even at 1 kHz, check your resistor tolerances and your oscilloscope probe compensation. More importantly, verify your power supply rails. If you are running a single-supply circuit without a mid-rail virtual ground bias, the bottom half of your AC waveform is clipping against 0V, which a standard multimeter will misinterpret as a lower RMS voltage, making it appear as though the gain is reduced.
Can I use a potentiometer to make an adjustable gain of op amp circuit?
Yes, but placement matters. Do not replace Rf with a potentiometer. If the wiper of the Rf potentiometer loses contact (an open circuit), the feedback loop breaks, and the output will violently rail, potentially damaging downstream components. Instead, replace Rg with a fixed resistor in series with a potentiometer. If the potentiometer wiper opens, Rg simply becomes infinite, the gain safely drops to 1 (unity buffer), and the circuit remains stable. Always place a fixed "stopper" resistor in series with the pot to prevent Rg from reaching 0Ω, which would cause the gain to approach infinity and rail the output.
