The formula of capacitance in series calculates the equivalent capacitance ($C_{eq}$) by summing the reciprocals of individual capacitors: $1/C_{eq} = 1/C_1 + 1/C_2 + ... + 1/C_n$. Unlike resistors, adding capacitors in series reduces the total capacitance while increasing the maximum voltage rating. This topology is critical when you need to block high DC voltages, build high-voltage snubber networks, or create AC coupling dividers where a single capacitor's voltage rating is insufficient for the bus voltage.

The Formula of Capacitance in Series and Node Topology

When capacitors are placed in series, the physical distance between the outermost plates effectively increases, which decreases the overall capacitance. However, the applied voltage divides across the dielectric of each component.

The Product-Over-Sum Shortcut: For exactly two capacitors in series, skip the reciprocals and use the product-over-sum formula:
$C_{eq} = (C_1 \times C_2) / (C_1 + C_2)$. If $C_1 = C_2$, the total capacitance is simply half of one capacitor's value.

Topology and Node Labels

Consider a standard two-capacitor series string. We define three critical nodes:

  • Node A (Source): The high-voltage input terminal connected to the anode of $C_1$.
  • Node B (Midpoint): The floating junction connecting the cathode of $C_1$ to the anode of $C_2$.
  • Node C (Return): The ground or low-side terminal connected to the cathode of $C_2$.

Because capacitance drops as you add series elements, engineers must carefully select starting values to ensure the final $C_{eq}$ meets the circuit's ripple or timing requirements. Below is a behavior table demonstrating how $C_{eq}$ and voltage ratings scale using standard 220µF, 250V aluminum electrolytic capacitors (e.g., Nichicon UHE series).

Configuration C1 Value C2 Value C3 Value Total Capacitance ($C_{eq}$) Ideal Max Voltage
Single (Baseline) 220µF - - 220µF 250V
2 in Series 220µF 220µF - 110µF 500V
3 in Series 220µF 220µF 220µF 73.3µF 750V
4 in Series 220µF 220µF 220µF (x2) 55µF 1000V

Source standard: Capacitance calculations follow IEC 60384-1 principles for fixed capacitors. Voltage ratings assume ideal, perfectly matched leakage currents.

Series vs. Parallel: Why Choose Series and Failure Modes

Why use the series formula of capacitance instead of just buying a higher-voltage capacitor or wiring them in parallel? Parallel wiring increases capacitance but maintains the exact same voltage rating as a single cell. You choose the series topology strictly for voltage endurance or to create a specific capacitive voltage divider for AC signal coupling. High-voltage DC bus snubbers (e.g., in 400V variable frequency drives) frequently use series strings because 500V+ snap-in electrolytic capacitors are physically massive, expensive, and have limited availability compared to standard 250V or 400V parts.

Failure Mode Contrast: What Breaks at the Extremes?

Understanding failure modes is where textbook theory meets bench reality. If a component fails in a series string, the results are often catastrophic due to the voltage redistribution.

  • If $C_1$ Shorts (Node A connects to Node B): The full bus voltage is instantly applied across $C_2$. If the bus is 450V and $C_2$ is rated for 250V, $C_2$ will experience severe overvoltage. The dielectric breaks down, internal pressure spikes, and the capacitor vents or explodes. This cascade failure is why series strings require balancing resistors.
  • If $C_1$ Opens (Internal connection breaks): The circuit path is broken. $C_{eq}$ drops to 0µF. No DC current flows, and Node B floats. The circuit safely fails open, but the snubber or filter ceases to function, potentially allowing destructive voltage transients to pass downstream.
  • Parallel Contrast: If a capacitor shorts in a parallel bank, it creates a dead short across the entire power supply, tripping the breaker or blowing the main fuse immediately.

Design Walkthrough: Sizing a 400V DC Bus Snubber

Let's design a real snubber network for a 400V DC bus. We need at least 100µF of capacitance to absorb switching transients, but our bus can spike to 450V. A single 450V capacitor is too large for our PCB footprint. We will use two 220µF, 250V capacitors in series.

Step 1: Verify Capacitance and Voltage

Using the formula of capacitance in series:
$C_{eq} = (220 \times 220) / (220 + 220) = 110\mu F$.
This satisfies our 100µF minimum. The ideal voltage rating is $250V + 250V = 500V$, giving us a safe 50V margin above our 450V maximum spike.

Step 2: Calculate Voltage Balancing (Bleeder) Resistors

Electrolytic capacitors have internal leakage currents that vary wildly from part to part, even from the same manufacturing batch. According to Nichicon's general specifications, leakage current can be estimated as $I = 0.01CV$ or 3µA, whichever is greater. For a 220µF/250V cap, leakage could reach 55µA. If $C_1$ leaks 10µA and $C_2$ leaks 50µA, $C_1$ will charge to a much higher voltage than $C_2$, eventually exceeding its 250V rating.

To fix this, we place high-value resistors in parallel with each capacitor to force equal voltage division. We want the resistor current to be at least 10 times the worst-case leakage current. Let's target 1mA of bleeder current per resistor.

  • Resistance: $R = V / I = 250V / 0.001A = 250,000\Omega$. The closest standard E24 value is 240kΩ.
  • Power Dissipation: $P = V^2 / R = 250^2 / 240,000 = 0.26W$. We must select 1/2W metal film resistors (e.g., Yageo MFR-25) to provide a safe thermal margin. Do not use 1/4W resistors here; they will overheat and drift.
Safety Warning: A 400V DC bus stores lethal energy. Even after power is removed, the 110µF equivalent capacitance can hold a fatal charge for minutes. Always design an active or passive discharge path that brings the voltage below 50V within 60 seconds of power-off, and verify with a CAT III rated multimeter before touching Node A, B, or C.

Breadboard-Testing and Verification Protocol

Before soldering this series string into a high-voltage PCB, validate the voltage division on the bench. Do not apply 400V immediately. Follow this step-by-step verification sequence using a variable DC power supply.

  1. Pre-Test LCR Measurement: Use a bench LCR meter (set to 120Hz, series equivalent circuit mode) to measure $C_1$ and $C_2$ individually. Record the exact values. A 20% tolerance means your '220µF' caps might actually be 190µF and 240µF, which slightly skews the natural voltage division.
  2. Wire the Nodes: On a high-voltage rated breadboard (or terminal strip), wire Node A to $C_1$ anode, $C_1$ cathode to Node B, Node B to $C_2$ anode, and $C_2$ cathode to Node C. Solder the 240kΩ 1/2W resistors directly across the leads of each capacitor.
  3. Low-Voltage Validation: Set your DC power supply to 12V. Connect it across Node A and Node C. Use a multimeter to measure the voltage at Node B relative to Node C. It should read exactly 6V (±0.2V). This confirms the resistors are functioning and the basic topology is correct.
  4. Ramp and Monitor: Increase the supply voltage in 50V increments. At each step, measure the voltage across $C_1$ (Node A to B) and $C_2$ (Node B to C). The voltages should remain within 5% of each other. If one capacitor consistently reads 15% higher voltage than the other, your leakage current mismatch is too high for the chosen bleeder resistors; decrease the resistor value to 180kΩ (which increases bleeder current to ~1.3mA).
  5. Discharge Verification: Turn off the power supply. Start a timer and measure Node A to C. Verify that the bleeder resistors discharge the string below 5V within your required safety timeframe (typically < 60 seconds for IEC 62368-1 compliance).

By strictly applying the formula of capacitance in series and engineering around the physical realities of leakage current and failure cascades, you can reliably build high-voltage networks using low-cost, readily available standard components. For deeper reading on capacitor derating and high-frequency impedance characteristics, refer to the Cornell Dubilier Aluminum Electrolytic Application Guide or standard circuit theory texts like All About Circuits.