When a textbook, exam, or schematic asks you to "find the voltage gain of the op-amp circuit shown," you are almost always looking at either an inverting or non-inverting configuration. Assuming the classic non-inverting topology—where the input signal feeds the positive terminal and the feedback network routes to the negative terminal—the direct answer for the closed-loop voltage gain ($A_v$) is $A_v = 1 + (R_f / R_i)$. If your feedback resistor ($R_f$) is 10kΩ and your ground-referenced resistor ($R_i$) is 1kΩ, your voltage gain is exactly 11 V/V.
While the math is straightforward, real-world bench behavior deviates from ideal textbook models due to input bias currents, bandwidth limits, and parasitic capacitance. Below, we break down the node analysis, select real-world components like the Texas Instruments TL072, map out failure modes, and walk through a step-by-step breadboard verification.
Topology Breakdown: Node Labels and the Golden Rules
To rigorously find the voltage gain of the op-amp circuit shown, we must first label our nodes and apply the two "golden rules" of ideal operational amplifiers operating in a closed negative feedback loop:
- Node A ($V_+$): The non-inverting input. Connected directly to the input signal ($V_{in}$).
- Node B ($V_-$): The inverting input. Connected to the junction of the feedback resistor ($R_f$) and the ground-referenced resistor ($R_i$).
- Node C ($V_{out}$): The output terminal, driving the load and feeding back through $R_f$.
The first golden rule states that an ideal op-amp has infinite input impedance, meaning zero current flows into Node A or Node B. The second golden rule states that negative feedback forces the differential input voltage to zero, creating a "virtual short" where $V_+ = V_-$.
Because Node A is tied to $V_{in}$, we know $V_+ = V_{in}$. By the virtual short rule, Node B must also sit at $V_{in}$. Node B is also the midpoint of a voltage divider formed by $R_f$ and $R_i$ connected between $V_{out}$ and ground. Therefore, the voltage at Node B is:
$V_- = V_{out} \times [R_i / (R_i + R_f)]$
Substituting $V_{in}$ for $V_-$ and rearranging the equation to solve for $V_{out} / V_{in}$ yields the standard non-inverting gain formula: $A_v = 1 + (R_f / R_i)$. Notice that the gain can never be less than 1. If you need attenuation (gain < 1), you must place a passive voltage divider ahead of the non-inverting input.
Component Selection and Behavior Matrix
Theory assumes perfect components, but bench reality requires selecting specific resistor tolerances and op-amp silicon. For a general-purpose audio or sensor amplification stage, the Texas Instruments TL072 is a staple JFET-input dual op-amp offering low noise and high slew rate. If you are operating from a single 5V supply, you would swap this for an LM358 or an MCP6002.
The table below maps exactly what happens to the circuit's behavior when you alter specific elements in a baseline design targeting a gain of 11 V/V (using $R_f$ = 10kΩ and $R_i$ = 1kΩ).
| Component Changed | New Value / Part | Effect on Voltage Gain | Effect on Bandwidth & Noise |
|---|---|---|---|
| Baseline (Control) | $R_f$ = 10kΩ, $R_i$ = 1kΩ (1% Metal Film) | 11 V/V (20.8 dB) | BW ≈ 272kHz; Noise ≈ 18nV/√Hz |
| $R_f$ increased | $R_f$ = 100kΩ, $R_i$ = 10kΩ | 11 V/V (Unchanged) | BW unchanged, but thermal noise increases by √10. Higher susceptibility to stray PCB capacitance. |
| $R_i$ shorted | $R_i$ = 0Ω (Jumper to GND) | 1 V/V (0 dB) - Voltage Follower | BW maximizes to full GBWP (3MHz). Lowest possible output impedance. |
| Op-Amp Swapped | TL072 replaced by OPA2134 | 11 V/V (Unchanged) | Noise drops to 8nV/√Hz. THD improves from 0.003% to 0.00008%. |
| Feedback Cap Added | 100pF MLCC in parallel with $R_f$ | 11 V/V at DC, rolls off at high freq | Creates a low-pass filter. -3dB point shifts to ~159kHz. Improves stability with capacitive loads. |
Why Non-Inverting Over Inverting? (And What Breaks at the Extremes)
When designing a front-end stage, you must choose between non-inverting and inverting topologies. The primary reason to choose the non-inverting configuration is input impedance. In an inverting amplifier, the input impedance is simply the value of the input resistor ($Z_{in} = R_i$). If you are buffering a high-impedance source like a piezoelectric vibration sensor, an electret microphone, or a passive guitar pickup, an inverting stage with a 10kΩ input resistor will severely load the source, causing signal attenuation and high-frequency roll-off before the signal even reaches the op-amp.
The non-inverting topology presents the op-amp's native common-mode input impedance to the source. For a JFET-input part like the TL072, this is typically $>10^{12}$ Ω. It will not load down almost any passive sensor.
Failure Mode Contrast: What Breaks at the Extremes?
Understanding how the circuit fails when a component goes open or short is critical for troubleshooting. Here is the failure-mode contrast for the feedback network:
- Short $R_f$ (0Ω): The output is directly tied to the inverting input. Gain drops to exactly 1 V/V. The circuit becomes a unity-gain buffer. This is a safe failure mode; the op-amp will not be damaged, but amplification is lost.
- Open $R_i$ (∞Ω): No current can flow to ground through the divider. The inverting input is pulled entirely to $V_{out}$. Gain drops to 1 V/V. Again, a safe failure mode resulting in a buffer.
- Short $R_i$ (0Ω): The inverting input is hard-tied to ground. The feedback fraction drops to zero. The op-amp operates in open-loop mode (gain > 100,000 V/V). The output will immediately slam into the positive supply rail ($V_{CC}$). If your signal has any negative swing, the output will rail back and forth, acting as a comparator.
- Open $R_f$ (∞Ω): The feedback loop is broken entirely. Just like shorting $R_i$, the op-amp enters open-loop comparator mode. The output will rail to $V_{CC}$ or $V_{EE}$ depending on whether $V_{in}$ is slightly above or below the voltage at the inverting input (which will float to 0V or pick up stray noise).
Step-by-Step Breadboard Testing and Verification
To verify the gain equation on the bench, we need to move from schematic to physical prototype. Solderless breadboards introduce parasitic capacitance (typically 2pF to 5pF between adjacent rows), which can cause high-frequency oscillation in fast op-amps if the layout is sloppy.
Tools Required: TL072CP DIP-8 IC, 10kΩ and 1kΩ 1% resistors, dual-output bench power supply, function generator, digital storage oscilloscope (DSO), and two 100nF MLCC decoupling capacitors.
- Establish Split Power Rails: Configure your bench power supply for ±12V. Connect +12V to the left red rail, -12V to the left blue rail, and tie the two ground terminals together to form a common 0V reference on the center black rail.
- Insert and Decouple the IC: Place the TL072 across the center trough. Connect Pin 8 to +12V and Pin 4 to -12V. Critical step: Place a 100nF ceramic capacitor directly across the power pins of the IC on the breadboard, as close to the plastic body as possible. This provides a local high-frequency charge reservoir and prevents power rail ringing.
- Wire the Feedback Network: Connect a 1kΩ resistor from Pin 2 (Inverting Input, Node B) to the ground rail. Connect a 10kΩ resistor from Pin 2 to Pin 1 (Output, Node C). Keep these leads short to minimize stray inductance.
- Route the Input Signal: Connect your function generator's output to Pin 3 (Non-Inverting Input, Node A). Ensure the function generator's ground is tied to your breadboard's common ground. Set the generator to a 1 kHz sine wave, 200mV peak-to-peak (100mV amplitude), with 0V DC offset.
- Measure and Calculate: Connect Oscilloscope Channel 1 to the input signal and Channel 2 to Pin 1. Trigger on Channel 1. Measure the peak-to-peak voltage of both channels. If Ch1 reads 200mVpp and Ch2 reads 2.20Vpp, your measured gain is $2.20 / 0.20 = 11.0$ V/V, perfectly matching the theoretical calculation.
Real-World Bandwidth and Slew Rate Limits
The equation $A_v = 1 + (R_f / R_i)$ assumes the op-amp can maintain this gain at any frequency. In reality, every voltage-feedback op-amp is bound by its Gain-Bandwidth Product (GBWP). According to the TL072 datasheet, the typical GBWP is 3 MHz.
Because GBWP is constant, your closed-loop bandwidth ($f_c$) is calculated as:
$f_c = GBWP / A_v = 3,000,000 / 11 \approx 272 \text{ kHz}$
If you attempt to amplify a 500 kHz signal with this circuit, the gain will have already rolled off by nearly half, and you will see significant phase shift between the input and output. For a comprehensive guide on how internal compensation capacitors dictate this limit, All About Circuits provides an excellent breakdown of dominant-pole compensation.
Furthermore, large-signal performance is limited by the slew rate—the maximum rate of change of the output voltage, measured in Volts per microsecond (V/µs). The TL072 has a slew rate of 13 V/µs. If you configure the circuit for a gain of 11 and apply a 1V amplitude (2Vpp) input, the output must swing 22Vpp (11V amplitude). The maximum frequency before the sine wave distorts into a triangle wave is dictated by the formula $f_{max} = \text{Slew Rate} / (2 \pi \times V_{peak})$. For an 11V peak output, $f_{max} = 13 / (2 \pi \times 11) \approx 188 \text{ kHz}$. Notice that the slew-rate limit (188 kHz) is actually lower than the small-signal bandwidth limit (272 kHz). When designing high-gain, high-voltage stages, always calculate both limits and design to the lower of the two.
