Field Effect Transistor (FET) symbols use a standardized visual language to define the device's channel type (N or P), operating mode (enhancement or depletion), and physical structure (JFET vs. MOSFET). The core identifier is the vertical channel line, the gate terminal, and the direction of the arrow, which dictates conventional current flow. Below is the master reference table for identifying these components on schematics, followed by practical bench advice for when silkscreen markings fail.
The Complete FET Symbol Reference Table
This table covers the most common discrete FETs you will encounter in power supplies, motor controllers, and logic-level switching circuits. Part examples are standard industry workhorses.
| Component Type | IEEE/ANSI Symbol Description | IEC 60617 Variant | Key Visual Identifier | Common Part Example |
|---|---|---|---|---|
| N-Channel JFET | Solid vertical channel line. Gate arrow points inward toward the channel. | Similar, but gate connection may be drawn at an angle without an explicit arrowhead in older drafts. | Arrow IN. Gate physically touches the channel line. | J111, 2N5457 |
| P-Channel JFET | Solid vertical channel line. Gate arrow points outward away from the channel. | Same as IEEE, arrow points out. | Arrow OUT. Gate physically touches the channel line. | J175, 2N5460 |
| N-Channel Enhancement MOSFET | Dashed vertical channel line. Arrow on the substrate/body points inward. | Encloses the symbol in a rectangular box; dashed line remains the key indicator. | Dashed line (normally OFF). Arrow IN. Gate is insulated (gap between gate and channel). | IRF520, 2N7000 |
| P-Channel Enhancement MOSFET | Dashed vertical channel line. Arrow on the substrate/body points outward. | Rectangular box enclosure; dashed line remains. | Dashed line (normally OFF). Arrow OUT. Insulated gate. | IRF9540, BSS84 |
| N-Channel Depletion MOSFET | Solid vertical channel line. Arrow on the substrate points inward. | Rectangular box enclosure; solid line remains. | Solid line (normally ON). Arrow IN. Insulated gate. | LND150, BSP149 |
| P-Channel Depletion MOSFET | Solid vertical channel line. Arrow on the substrate points outward. | Rectangular box enclosure; solid line remains. | Solid line (normally ON). Arrow OUT. Insulated gate. | Rare in discrete; mostly IC internals |
Rows People Get Wrong in Schematic Capture
When reading or drawing schematics in tools like KiCad or Altium, misinterpreting a single line style or arrow direction will result in a non-functional or shorted circuit. Here are the most common pitfalls:
Enhancement vs. Depletion (The Dashed vs. Solid Line)
The most critical mistake is confusing enhancement-mode and depletion-mode MOSFETs.
- Dashed Line = Enhancement Mode: The device is normally OFF. You must apply a gate-to-source voltage ($V_{GS}$) to "enhance" the channel and allow current to flow. This is what 95% of modern power switching circuits use (e.g., switching a 12V relay with an ESP32 GPIO via a 2N7000).
- Solid Line = Depletion Mode: The device is normally ON. Current flows with zero gate voltage, and you must apply $V_{GS}$ to "deplete" the channel and pinch it off. These are used in niche applications like constant-current sources or high-voltage linear regulators.
The Arrow Direction (N-Channel vs. P-Channel)
The arrow always resides on the substrate or body terminal, and it always indicates the direction of conventional current flow if the substrate diode were forward-biased.
- Arrow Pointing IN = N-Channel: Think "Not Pointing In" for P-channel to remember the inverse. N-channel devices switch the low side (connected to ground).
- Arrow Pointing OUT = P-Channel: P-channel devices switch the high side (connected to the positive supply rail).
The Insulated Gate Gap
If the gate line physically touches the vertical channel line, it is a JFET (Junction FET). The gate forms a PN junction with the channel. If there is a distinct gap or parallel line separating the gate from the channel, it is a MOSFET (Metal-Oxide-Semiconductor FET), indicating the gate is capacitively coupled and insulated by silicon dioxide. Applying DC voltage to a JFET gate expecting MOSFET behavior will result in massive gate current and a destroyed component.
IEEE vs IEC: Regional Standard Variants
Schematic standards vary by region, which causes confusion when collaborating across borders or reading legacy datasheets.
- IEEE 315 / ANSI Y32.2 (North America): The dominant standard in US/Canadian schematics. It relies on the "standalone" symbol style described in the table above, where the shape itself conveys the component type without an enclosure.
- IEC 60617 (Europe / International): The IEC standard prefers enclosing semiconductor devices within a rectangular bounding box. The internal lines (dashed/solid) and arrows remain the same, but the box signifies it is a solid-state semiconductor device. You will frequently see this in datasheets from STMicroelectronics, Infineon, and NXP.
If you are reading a schematic from a European manufacturer and see a simple rectangle with three terminals and no internal markings, check the bill of materials (BOM). Older IEC drafts sometimes omitted the internal FET geometry if the context was purely functional block-diagramming, though modern CAD libraries almost always enforce the internal dashed/solid lines.
Bench Identification for Faded or Missing Markings
When a power MOSFET blows up in a motor controller, the silkscreen on the TO-220 or SOT-23 package often burns off entirely. If you need to determine if the unmarked replacement should be N-channel or P-channel, use your multimeter's diode test mode.
- Set your DMM to Diode Test: The meter will output a small current and measure the forward voltage drop.
- Test for the Intrinsic Body Diode: Almost all discrete power MOSFETs have a parasitic body diode between the Drain and Source due to the manufacturing process.
- N-Channel Identification: Place the Red probe on the Source (middle pin on standard TO-220) and the Black probe on the Drain. You should read a forward voltage drop of roughly 0.4V to 0.6V. Reverse the probes, and the meter should read "OL" (Open Loop). The diode cathode is at the Drain.
- P-Channel Identification: Place the Black probe on the Source and the Red probe on the Drain. You will read the 0.4V - 0.6V drop. Reverse the probes for "OL". The diode anode is at the Drain.
- JFET Caveat: JFETs do not have this intrinsic body diode between Drain and Source. If you read "OL" in both directions across Drain and Source, but read a diode drop between the Gate and both Drain/Source, you are holding a JFET, not a MOSFET.
For deep-dive theory on the semiconductor physics dictating these symbols and parasitic structures, refer to the All About Circuits semiconductor textbook or the ON Semiconductor MOSFET Handbook.
FET Symbols FAQ
Why do some MOSFET symbols have four terminals instead of three?
A 4-terminal MOSFET symbol explicitly shows the "Bulk" or "Body" (B) connection separate from the Source (S). In physical discrete components (like a standard IRF3205), the manufacturer internally bonds the bulk to the source, so you only deal with three physical pins. However, in integrated circuit (IC) design and monolithic die layouts, the bulk must be tied to the most negative potential (for N-channel) or most positive potential (for P-channel) to keep the internal PN junctions reverse-biased. Schematic capture tools use the 4-terminal symbol to remind IC designers to route the substrate tie correctly.
How do I tell an N-channel from a P-channel FET symbol if the arrow is missing?
If a schematic is poorly drawn and the arrowhead on the substrate line is missing, look at the gate voltage polarity in the surrounding circuit. If the gate is driven by a positive voltage relative to ground (e.g., a 5V microcontroller GPIO or a 12V gate driver IC), it is almost certainly an N-channel enhancement MOSFET used as a low-side switch. If the gate is pulled down to ground to turn it on, and sits at the high-side rail voltage when off, it is a P-channel MOSFET. Contextual circuit analysis is your fallback when symbol drafting is sloppy.
What does the circle on the gate of a MOSFET symbol mean?
A circle on the gate terminal (similar to the inversion bubble on a logic gate) indicates an active-low or normally-ON behavior in a logical sense. While rare in discrete MOSFET symbols, you will see this in digital logic schematics representing CMOS inverters, or occasionally on depletion-mode MOSFET symbols in older literature to emphasize that a negative gate-to-source voltage is required to turn the device off. In standard modern IEEE practice, the solid vs. dashed channel line is the preferred method for denoting normally-ON vs normally-OFF, making the gate bubble redundant and largely deprecated for discrete FETs.
Are IGBT symbols considered FET symbols?
An IGBT (Insulated-Gate Bipolar Transistor) combines the insulated gate of a MOSFET with the bipolar current conduction of a BJT. Its symbol reflects this hybrid nature: it looks exactly like an N-channel or P-channel enhancement MOSFET (dashed line, insulated gate), but the Drain terminal is replaced by a "Collector" terminal featuring an arrow pointing inward or outward, exactly like a BJT. While they share the high-impedance gate drive characteristics of FETs, their internal physics and symbol terminals (Gate, Collector, Emitter) classify them as a distinct category in schematic standards.
