A field-effect transistor (FET) used as an amplifier is a circuit configuration where a small AC voltage applied to the high-impedance gate terminal controls a much larger current flowing through the drain-source channel, thereby producing an amplified, inverted voltage signal across a load resistor. What this changes in a real circuit is the signal amplitude without drawing significant continuous current from the source driving the gate, making it ideal for buffering high-impedance sensors and delicate audio stages. Beginners commonly confuse a FET amplifier with a bipolar junction transistor (BJT) amplifier, mistakenly assuming the FET's gate requires a continuous base-like bias current, when in reality, the gate draws virtually zero steady-state DC current.
The Core Mechanism: Voltage-Controlled Current
Unlike a BJT, which is a current-controlled device relying on minority carrier injection, a FET is a voltage-controlled device. The current flowing from drain to source ($I_D$) is modulated by the electric field generated by the gate-to-source voltage ($V_{GS}$). In a Junction FET (JFET), applying a reverse-bias voltage to the gate-channel PN junction widens the depletion region, physically 'pinching' the conductive channel and restricting current flow. In a MOSFET, the gate is insulated by a silicon dioxide layer, and the electric field attracts charge carriers to form an inversion layer channel.
The critical parameter that defines a FET's amplification capability is its transconductance ($g_m$). Transconductance is the ratio of the change in output drain current to the change in input gate voltage, measured in Siemens (S) or millisiemens (mS). A higher $g_m$ means a small wiggle in gate voltage produces a large swing in drain current. When this varying current passes through a drain load resistor ($R_D$), Ohm's law converts it back into a much larger voltage swing, achieving voltage gain.
Because the gate draws negligible DC current (only tiny leakage currents in the nanoamp or picoamp range), the input impedance of a FET amplifier is extraordinarily high—often in the megaohm or gigaohm range. This prevents the amplifier from 'loading down' weak signal sources, a concept known as impedance bridging, which is critical when interfacing with piezoelectric pickups or electret microphones.
Worked Example: Calculating Gain in a JFET Common-Source Stage
To understand how a FET acts as an amplifier in practice, let's calculate the voltage gain of a common-source JFET preamplifier using the widely available J211 N-channel JFET. We will assume a standard self-biasing configuration with a source bypass capacitor to maximize AC gain.
Assumptions & Datasheet Values (J211):
- Zero-gate voltage drain current ($I_{DSS}$): 4.0 mA (typical)
- Gate-source cutoff voltage ($V_P$ or $V_{GS(off)}$): -2.0 V
- Drain resistor ($R_D$): 4.7 kΩ
- Target DC bias gate-source voltage ($V_{GS}$): -1.0 V
Step 1: Calculate the DC Drain Current ($I_D$)
Using Shockley's equation for the saturation region:
$I_D = I_{DSS} \times (1 - \frac{V_{GS}}{V_P})^2$
$I_D = 4.0\text{ mA} \times (1 - \frac{-1.0\text{ V}}{-2.0\text{ V}})^2$
$I_D = 4.0\text{ mA} \times (1 - 0.5)^2 = 4.0\text{ mA} \times 0.25 = \mathbf{1.0\text{ mA}}$
Step 2: Calculate Maximum Transconductance ($g_{m0}$)
$g_{m0} = \frac{2 \times I_{DSS}}{|V_P|} = \frac{2 \times 4.0\text{ mA}}{2.0\text{ V}} = \mathbf{4.0\text{ mS}}$
Step 3: Calculate Actual Transconductance at Bias Point ($g_m$)
$g_m = g_{m0} \times (1 - \frac{V_{GS}}{V_P}) = 4.0\text{ mS} \times (1 - 0.5) = \mathbf{2.0\text{ mS}}$
Step 4: Calculate Voltage Gain ($A_v$)
Assuming the source resistor is fully bypassed by a capacitor (meaning AC source resistance is zero) and ignoring the FET's internal output resistance ($r_{ds}$) for simplicity:
$A_v = -g_m \times R_D$
$A_v = -2.0\text{ mS} \times 4.7\text{ k}\Omega = -2.0 \times 10^{-3} \times 4700 = \mathbf{-9.4}$
The negative sign indicates phase inversion. A 10 mV peak-to-peak audio signal at the gate will result in a 94 mV peak-to-peak signal at the drain, inverted by 180 degrees.
Where You Meet FET Amplifiers in Practice
You will rarely see a discrete FET amplifier in modern digital logic, but they dominate specific analog niches where their high input impedance and noise characteristics shine:
- Guitar Effects Pedals: The input buffer of a Tube Screamer or the gain stages in a Big Muff fuzz pedal frequently use JFETs (like the J201 or 2N5457) because their soft clipping characteristics mimic vacuum tubes, and their high input impedance preserves the high-frequency content of passive magnetic guitar pickups.
- RF Front-Ends: The J310 is a legendary N-channel JFET used in FM radio receivers and software-defined radio (SDR) preselectors. Its low gate-drain capacitance allows it to amplify VHF signals (up to 400 MHz) without oscillating or suffering from severe Miller effect degradation.
- Oscilloscope Input Buffers: If you look at the input stage of a bench oscilloscope or a high-end multimeter, you will find JFET-input operational amplifiers like the TL072 or OPA1642. The FET input ensures the meter does not load the circuit under test, maintaining measurement accuracy on high-impedance voltage dividers.
- Electret Microphone Preamps: The tiny capsule inside an electret condenser microphone actually contains a microscopic JFET wired as a common-drain (source follower) impedance converter, stepping down the massive impedance of the capacitor diaphragm to a level that can travel down a standard XLR cable.
BJT vs. FET: Choosing the Right Transistor for the Job
Deciding between a Bipolar Junction Transistor and a Field-Effect Transistor depends entirely on the source impedance, frequency, and noise requirements of your circuit. Below is a direct comparison of standard small-signal variants.
| Characteristic | BJT (e.g., 2N3904) | JFET (e.g., J211) | MOSFET (e.g., 2N7000) |
|---|---|---|---|
| Input Impedance | Low (1kΩ - 50kΩ) | Very High (1MΩ - 100MΩ) | Extremely High (>1GΩ) |
| Control Variable | Base Current ($I_B$) | Gate Voltage ($V_{GS}$) | Gate Voltage ($V_{GS}$) |
| Low-Frequency (1/f) Noise | Moderate | Very Low | High |
| Thermal Runaway Risk | High (requires emitter degeneration) | Low (negative temp coefficient at high $I_D$) | Low (but threshold shifts with heat) |
| Primary Use Case | General purpose switching, low-impedance audio | High-impedance audio buffers, RF front-ends | Digital logic level shifting, power switching |
For a deep dive into how semiconductor manufacturers optimize these geometries, the Electronics Tutorials guide on FET amplifiers provides excellent schematic breakdowns of biasing networks. Furthermore, Analog Devices details the specific noise advantages of FET-input op-amps in high-precision sensor conditioning.
Frequently Asked Questions
Can I use a power MOSFET like an IRF520 as a small-signal amplifier?
Technically yes, but practically it is a terrible choice. Power MOSFETs like the IRF520 are optimized for low $R_{DS(on)}$ and high current handling, which requires a massive silicon die area. This massive area results in very high internal parasitic capacitances, specifically the reverse transfer capacitance ($C_{rss}$ or Miller capacitance). In a linear amplifier configuration, this capacitance is multiplied by the circuit's voltage gain, creating a low-pass filter that will severely roll off high frequencies and likely cause high-frequency parasitic oscillation. Additionally, the threshold voltage ($V_{GS(th)}$) variance on power MOSFETs is wide (often 2V to 4V), making stable DC biasing incredibly difficult without a feedback network. Stick to small-signal MOSFETs (like the BS170) or JFETs for linear amplification.
Why does my common-source FET amplifier output an inverted signal?
The 180-degree phase inversion is a fundamental result of how the load resistor interacts with the FET's channel. When the AC input signal at the gate goes positive, the channel opens wider, allowing more drain current ($I_D$) to flow. This increased current flows through the drain resistor ($R_D$), creating a larger voltage drop across it according to Ohm's Law ($V = I \times R$). Because the supply voltage ($V_{DD}$) is fixed, a larger voltage drop across $R_D$ forces the voltage at the drain node (your output) to drop closer to ground. Therefore, a positive swing at the input results in a negative swing at the output.
What causes the 'Miller Effect' in a FET amplifier, and how do I fix it?
The Miller Effect occurs because there is a small physical parasitic capacitance between the gate and the drain ($C_{gd}$) inside the FET package. Because the drain voltage is an amplified, inverted copy of the gate voltage, the voltage difference across this tiny capacitor is much larger than the input signal alone. This makes the capacitor appear to the input source as if it were multiplied by the gain of the amplifier ($C_{Miller} \approx C_{gd} \times (1 + |A_v|)$). This massive apparent capacitance shunts high-frequency signals to ground, killing your bandwidth. To fix this in RF or high-speed audio designs, engineers use a cascode configuration. A cascode places a common-gate transistor on top of the common-source transistor, holding the drain voltage of the bottom FET virtually constant. With no voltage swing at the drain of the input FET, the Miller multiplication drops to near zero, restoring high-frequency bandwidth.
