A FET as an amplifier uses a small voltage applied to its gate to control a much larger current flowing from drain to source, thereby reproducing a weak input signal at a higher voltage level. In a real circuit, it changes a high-impedance, low-voltage signal (like a piezo sensor or electret microphone) into a robust, low-impedance signal capable of driving an ADC or subsequent gain stage without loading down the source. Designers commonly confuse the FET’s "saturation" region with a BJT’s "saturation" region; in a BJT, saturation means fully ON (acting as a switch), but in a FET, the saturation region (often called the active region in datasheets) is where linear amplification actually occurs.
The Core Mechanism: Transconductance and the Saturation Region
Unlike Bipolar Junction Transistors (BJTs) which are current-controlled devices, Field Effect Transistors (FETs) are voltage-controlled. The gate draws virtually zero steady-state DC current, making the input impedance astronomically high—often >10^9 ohms for MOSFETs and >10^12 ohms for JFETs.
The amplification capability is defined by transconductance ($g_m$), measured in Siemens (S) or milli-Siemens (mS). It dictates how much the drain current ($I_D$) changes for a given change in gate-to-source voltage ($V_{GS}$). Think of the gate voltage as the handle on a high-pressure water valve: a tiny rotational movement of the handle (voltage) dictates a massive change in water flow (current) through the pipe.
Worked Numeric Example: Biasing a 2N7000 Common Source Amplifier
To use a FET as an amplifier, you must establish a DC Quiescent Point (Q-point) in the middle of its saturation region so the AC signal can swing positively and negatively without hitting the supply rails or dropping into the ohmic (triode) region. Let us calculate the bias for a standard Common Source amplifier using a 2N7000.
Circuit Parameters:
- Supply Voltage ($V_{DD}$): 12.0V
- Voltage Divider: $R_1 = 1.0 M\Omega$ (top), $R_2 = 330 k\Omega$ (bottom)
- Source Resistors: $R_{S1} = 470 \Omega$ (bypassed with 10µF cap), $R_{S2} = 1.0 k\Omega$ (unbypassed for AC stability)
- Drain Resistor ($R_D$): $4.7 k\Omega$
Step-by-Step DC Bias Calculation:
- Gate Voltage ($V_G$): The voltage divider sets $V_G = 12V \times [330k / (1000k + 330k)] = 2.97V$.
- Source Voltage ($V_S$): Assuming a typical $V_{GS}$ of 2.5V for our target drain current, $V_S = V_G - V_{GS} = 2.97V - 2.5V = 0.47V$.
- Drain Current ($I_D$): Since $I_D \approx I_S$, and $I_S = V_S / R_{S1} = 0.47V / 470\Omega = 1.0 mA$.
- Drain Voltage ($V_D$): The drop across $R_D$ is $1.0 mA \times 4.7 k\Omega = 4.7V$. Therefore, $V_D = 12V - 4.7V = 7.3V$.
- Drain-to-Source Voltage ($V_{DS}$): $V_{DS} = V_D - V_S = 7.3V - 0.47V = 6.83V$.
Verifying Saturation and AC Gain:
To remain in saturation, $V_{DS}$ must be greater than $V_{GS} - V_{GS(th)}$. Assuming $V_{GS(th)}$ is 2.1V, the overdrive voltage is $0.4V$. Since $6.83V \gg 0.4V$, the FET is deeply in the saturation region. The AC voltage gain ($A_v$) is dominated by the unbypassed source resistor $R_{S2}$, yielding $A_v \approx -R_D / R_{S2} = -4700 / 1000 = -4.7$. The negative sign indicates a 180-degree phase inversion.
Where You Meet This in Practice
You will rarely use a discrete FET amplifier for high-fidelity audio power stages—op-amps and Class D ICs handle that. Instead, FET amplifiers dominate at the very front end of signal chains where impedance matching is critical:
- Piezo Electric Pickups: Acoustic guitar piezo sensors have an output impedance in the mega-ohm range. A BJT would load them down, killing the bass response. A JFET common-drain (source follower) buffers the signal perfectly.
- Electret Microphone Preamps: The internal capsule of an electret mic contains a tiny JFET configured as a common-source amplifier to convert the high-impedance capsule capacitance changes into a usable low-impedance current.
- High-Z Scientific Sensors: pH probes, EMG (muscle) sensors, and capacitive humidity sensors rely on MOSFET input stages to measure voltage without drawing the picoamp-level currents that would skew the chemical or biological readings.
Bench Scenario Walkthrough: The Clipped Output Disaster
The Setup: A hobbyist is building a boutique guitar overdrive pedal using a J210 N-channel JFET in a common-source configuration. The schematic calls for a $12V$ supply, a $10k\Omega$ drain resistor, and a $1k\Omega$ source resistor. The expected AC gain is roughly 10, and the input signal is a $100mV_{pp}$ sine wave from a function generator.
The Numbers: The builder expects $1.0V_{pp}$ at the drain. Instead, the oscilloscope shows the output flat-topping (clipping) severely on the positive peaks at just $0.6V_{pp}$, while the negative peaks look clean.
The Outcome & What Went Wrong: The builder assumed the J210 had a specific $I_{DSS}$ (zero-gate-voltage drain current) of $50mA$, as printed on a generic forum post. In reality, JFETs have massive $I_{DSS}$ binning spreads; the specific part in the breadboard had an $I_{DSS}$ of $25mA$. This lower current shifted the DC Q-point dangerously close to the supply rail. When the AC signal swung positive on the gate, the JFET entered the ohmic (triode) region, acting like a closed switch rather than an amplifier, resulting in hard clipping. The fix: The builder replaced the fixed source resistor with a $5k\Omega$ trimmer potentiometer, adjusted it while monitoring the drain DC voltage to sit exactly at $6.0V$ (half of $V_{DD}$), and the clipping vanished. Always use source degeneration or active biasing with JFETs to compensate for part-to-part variance.
Common FET Amplifier Configurations Compared
| Configuration | Input Terminal | Output Terminal | Voltage Gain | Phase Shift | Primary Use Case |
|---|---|---|---|---|---|
| Common Source | Gate | Drain | High (Inverting) | 180° | General voltage amplification, sensor preamps |
| Common Drain (Source Follower) | Gate | Source | ~1 (Unity) | 0° | Impedance buffering, driving low-Z loads |
| Common Gate | Source | Drain | High (Non-inverting) | 0° | High-frequency RF amps, current buffers |
FAQ: FET Amplifier Troubleshooting
Q: Why is my high-frequency gain rolling off much faster than my calculations predict?
A: You are likely hitting the Miller Effect. In a common-source amplifier, the parasitic gate-to-drain capacitance ($C_{gd}$) is effectively multiplied by the voltage gain. If your FET has a $C_{gd}$ of 5pF and your gain is 50, the input sees an effective capacitance of 255pF. Combined with your high-impedance gate biasing resistors, this forms a low-pass filter. To fix this, lower your gate biasing resistor values or switch to a cascode topology.
Q: Should I use a MOSFET or a JFET for small-signal audio amplification?
A: For discrete, low-noise audio front-ends, JFETs (like the 2SK170 or J210) are generally preferred. Their transfer characteristic ($I_D$ vs $V_{GS}$) is a smooth square-law curve, which produces softer, more musical even-order harmonic distortion when pushed into clipping. Enhancement-mode MOSFETs (like the BS170) have a sharper threshold "knee" and higher gate capacitance, making them better suited for switching or higher-frequency RF applications.
Q: My FET amplifier is oscillating at RF frequencies. How do I stop it?
A: High-gain FET stages are notoriously prone to parasitic oscillation due to lead inductance and stray capacitance. Add a small "gate stopper" resistor (typically $100\Omega$ to $470\Omega$) physically as close to the gate pin as possible. This resistor dampens the LC tank circuit formed by the gate capacitance and the PCB trace inductance without affecting the audio or low-frequency signal gain.
References and further reading:
1. Electronics Tutorials: MOSFET Amplifier Basics
2. Analog Devices: Designing with JFETs
3. All About Circuits: Introduction to Field Effect Transistors
