The exclusive NOR (XNOR) gate is a digital logic gate that outputs a HIGH (1) only when both inputs match—either both HIGH or both LOW. Recognizing the exclusive nor gate symbol on a schematic is your first step to debugging parity checkers, digital comparators, and phase detectors. Unlike standard gates, the XNOR acts as an equality detector, making it indispensable in error-checking circuits and arithmetic logic units (ALUs).
Because logic schematics vary by region and era, misidentifying the symbol can lead to catastrophic wiring errors. Below is the immediate breakdown of how this gate is represented across global standards, followed by the physical IC pinouts you need at the bench.
Standard Symbol Variants: ANSI/IEEE vs. IEC 60617
The visual representation of the XNOR gate depends entirely on the drafting standard used by the engineer. In the US, you will almost exclusively see the ANSI/IEEE distinctive shape. In Europe and international industrial documentation, the IEC rectangular format dominates. Legacy equipment may still feature the German DIN standard.
| Standard | Visual Description | Logic Expression | Region / Primary Usage |
|---|---|---|---|
| ANSI/IEEE 91a | D-shaped XOR body with a double curved line on the input side, plus a negation bubble on the output. | Y = A ⊙ B or Y = (A ⊕ B)' |
North America, US military, academic textbooks. |
| IEC 60617 | Rectangular box with "=1" inside (indicating XOR), plus a negation circle on the output pin. | Y = ¬(A ⊕ B) | Europe, international industrial automation, IEC-compliant PLC schematics. |
| DIN 40700 | A distinct geometric shape resembling a shield or arrowhead with an output bubble (largely obsolete). | Y = A ≡ B | Legacy German engineering, older Siemens/Bosch industrial prints. |
| MIL-STD-806 | Similar to ANSI but strictly enforces the "bubble" placement rules for active-low signals. | Y = A XNOR B | US Defense, aerospace avionics schematics. |
Key Identification Tip: The ANSI symbol's double curved line on the input is the primary visual differentiator from a standard NOR gate. If you see the double curve but no output bubble, you are looking at an XOR gate. The bubble inverts the logic, creating the XNOR.
14-Pin DIP IC Pinouts and Truth Tables
When moving from schematic to breadboard, you will typically reach for a Quad 2-Input XNOR IC. The two most common bench staples are the 74HC266 (High-speed CMOS, open-drain) and the CD4077 (Standard CMOS, push-pull). Both share the industry-standard 14-pin Dual In-line Package (DIP) footprint, but their internal output architectures differ wildly.
| Pin Number | Function / Signal | Description |
|---|---|---|
| 1 | 1A | Input A of Gate 1 |
| 2 | 1B | Input B of Gate 1 |
| 3 | 1Y | Output of Gate 1 |
| 4 | 2Y | Output of Gate 2 |
| 5 | 2A | Input A of Gate 2 |
| 6 | 2B | Input B of Gate 2 |
| 7 | GND | Ground (0V reference) |
| 8 | 3Y | Output of Gate 3 |
| 9 | 3A | Input A of Gate 3 |
| 10 | 3B | Input B of Gate 3 |
| 11 | 4Y | Output of Gate 4 |
| 12 | 4A | Input A of Gate 4 |
| 13 | 4B | Input B of Gate 4 |
| 14 | VCC | Positive Supply Voltage (See IC specific limits) |
The Truth Table
The XNOR gate is fundamentally an equality checker. The output is HIGH if and only if Input A equals Input B.
| Input A | Input B | Output Y (XNOR) |
|---|---|---|
| 0 (LOW) | 0 (LOW) | 1 (HIGH) |
| 0 (LOW) | 1 (HIGH) | 0 (LOW) |
| 1 (HIGH) | 0 (LOW) | 0 (LOW) |
| 1 (HIGH) | 1 (HIGH) | 1 (HIGH) |
Voltage Specifications: The CD4077 operates from 3V to 15V, making it ideal for battery-powered 9V or 12V projects. The 74HC266 is strictly a 2V to 6V part; feeding it 12V will instantly destroy the silicon. Always verify the VCC rating on the datasheet before applying power.
Schematic Pitfalls: Rows People Get Wrong and Faded Markings
Even experienced technicians misread logic diagrams when fatigue sets in or when dealing with degraded documentation. Here is how to avoid the most common errors.
The 'Rows People Get Wrong' Notes
- The 0,0 Output Trap: When reading the truth table, hobbyists frequently assume that "no input voltage" means "no output voltage." They forget that the XNOR outputs a HIGH when both inputs are LOW. If you are using an XNOR to trigger a relay when two limit switches are open (LOW), the relay will energize. Design your fail-safes accordingly.
- IEC "=1" vs "1" Confusion: In IEC schematics, an OR gate is marked with a "1" inside the rectangle. An XOR gate is marked with "=1". An XNOR is "=1" with an output bubble. If the schematic is printed poorly, the "=" sign can look like a smudge, causing you to misidentify an XNOR as a standard OR gate. Always look for the output negation bubble to confirm.
- Active-Low Bubble Placement: In MIL-STD schematics, bubbles indicate active-low logic states, not just inversion. An XNOR gate might be drawn as an XOR symbol with bubbles on the inputs rather than the output. Logically, it behaves identically, but wiring it without understanding the active-low intent can cause phase errors in clock circuits.
Safe Interpretation When Markings are Faded or Missing
If you are repairing legacy gear and the IC silkscreen is rubbed off, or the schematic ink is faded beyond recognition, do not guess. Use a logic probe or multimeter to deduce the gate type safely while the circuit is powered at its nominal logic voltage (e.g., 5V).
- Step 1: Identify VCC and GND pins (usually top-left and bottom-right corners for 14-pin DIPs, but verify with a continuity test to ground planes while unpowered).
- Step 2: Power the board. Tie both inputs of the unknown gate to GND (0,0).
- Step 3: Measure the output. If the output is HIGH, the gate is either an XNOR or a NOR gate.
- Step 4: Tie Input A to VCC (HIGH) and Input B to GND (LOW). If the output drops to LOW, it is still either XNOR or NOR.
- Step 5 (The Tie-Breaker): Tie both inputs to VCC (1,1). If the output goes HIGH, you have an XNOR gate. If the output stays LOW, it is a NOR gate.
Real-World Bench Wiring and the Open-Collector Trap
The most common reason a newly built XNOR circuit fails on the bench is the open-collector (or open-drain) trap. If you consult the Texas Instruments SN74HC266 datasheet, you will note that the outputs are not standard push-pull CMOS. They are open-drain.
This means the IC can pull the output line to GND (LOW), but it cannot drive it to VCC (HIGH). If you wire an LED or a microcontroller input directly to the output pin of a 74HC266 or 74LS266, the HIGH state will simply float, resulting in erratic readings or dim, ghosting LEDs.
The Fix: You must install a pull-up resistor between the output pin and VCC. For standard 5V TTL/CMOS logic driving a microcontroller GPIO, a 4.7kΩ to 10kΩ resistor is ideal. If you are driving an LED directly, calculate the resistor based on the LED forward voltage, but ensure it connects to VCC, not GND.
Conversely, if you use the CD4077, the outputs are standard push-pull. They can source and sink current directly without pull-up resistors. However, the CD4077 has much lower drive capability (typically ~6mA at 5V) compared to the 74-series parts. Always match the IC architecture to your load requirements.
Finally, never skip decoupling. Place a 100nF (0.1µF) ceramic capacitor as close to the IC as physically possible, bridging Pin 14 (VCC) and Pin 7 (GND). Digital gates switch in nanoseconds, drawing sharp spikes of current from the power rail. Without local capacitance, the voltage droop will cause the XNOR gate to output false parity errors, a phenomenon thoroughly documented in the TI Logic Guide. Proper decoupling ensures your equality detector stays equal.
