The EX-NOR gate boolean expression defines a digital logic operation that outputs a HIGH (1) state only when all inputs share the identical logic level, mathematically written as Y = AB + A'B'. Also known as the Exclusive-NOR or equivalence gate, it is the logical complement of the XOR gate. In a physical circuit, inserting an EX-NOR gate (like a standard 74HC266 IC) changes the system from a 'difference detector' to an 'equality detector,' altering downstream triggers to fire only when signal states match rather than diverge. Beginners frequently confuse the EX-NOR expression with a standard OR gate; a standard OR outputs HIGH if any input is HIGH, whereas EX-NOR strictly requires matching inputs to output a HIGH state.
The Core EX-NOR Gate Boolean Expression and Truth Table
At the bench, you will rarely see the boolean algebra written out in raw text; instead, you will see the XNOR symbol (an XOR gate with an inversion bubble on the output). However, understanding the underlying algebra is critical when you need to optimize logic in an FPGA or CPLD, or when you are forced to build the gate from discrete NAND/NOR transistors.
The standard 2-input EX-NOR gate boolean expression is:
Y = A ⊙ B = AB + A'B'
This reads as: 'Y is true if (A AND B) OR (NOT A AND NOT B)'. It is the sum of the minterms where the inputs are identical.
| Input A | Input B | A ⊕ B (XOR) | Y = A ⊙ B (EX-NOR) |
|---|---|---|---|
| 0 (LOW) | 0 (LOW) | 0 | 1 (HIGH) |
| 0 (LOW) | 1 (HIGH) | 1 | 0 (LOW) |
| 1 (HIGH) | 0 (LOW) | 1 | 0 (LOW) |
| 1 (HIGH) | 1 (HIGH) | 0 | 1 (HIGH) |
When using a CMOS IC like the Texas Instruments 74HC series, remember that logic levels are not just 0V and 5V. At a 5V supply, the guaranteed HIGH input threshold (V_IH) is 3.15V, and the LOW threshold (V_IL) is 1.35V. If your input signal lingers between 1.35V and 3.15V, the EX-NOR gate will enter its linear region, drawing excessive quiescent current and potentially overheating the die.
Worked Numeric Example: 2-Bit Equality Detection
Let us look at a real-world scenario: designing a 2-bit digital comparator to check if two binary numbers (A1A0 and B1B0) are identical. We will use a TI SN74HC266 (Quad 2-input EX-NOR with open-drain outputs) and an SN74HC08 (Quad 2-input AND gate).
The Logic Setup:
- EX-NOR Gate 1 compares A0 and B0. Output: X0 = A0 ⊙ B0
- EX-NOR Gate 2 compares A1 and B1. Output: X1 = A1 ⊙ B1
- AND Gate compares X0 and X1. Final Output: Y = X0 · X1
Calculating Propagation Delay (t_pd):
According to the SN74HC266 datasheet at V_CC = 5V and 25°C, the typical propagation delay is 18 ns, with a maximum of 25 ns. The SN74HC08 AND gate also has a typical t_pd of 18 ns. Because the signals must pass through the EX-NOR gate and then the AND gate in series, the total worst-case propagation delay for the equality signal is 25 ns + 25 ns = 50 ns maximum. If your microcontroller is sampling this output on a 40 MHz clock (25 ns period), you will miss the signal edge due to this cumulative delay. You must either lower the clock speed or use a dedicated comparator IC like the 74HC85.
Calculating Power Dissipation:
The maximum quiescent supply current (I_CC) for the 74HC266 is 80 µA at 5V. The power dissipated by the IC in a static state is P = V × I = 5V × 80 µA = 400 µW. However, if you leave any of the unused inputs on the quad package floating, the CMOS input buffers will oscillate, spiking the current draw to several milliamps and draining your battery. Always tie unused inputs to V_CC or GND.
Where You Meet This in Practice
You will not often wire up discrete EX-NOR gates for simple microcontroller projects, as the MCU can handle boolean equivalence in a single clock cycle via software. However, the EX-NOR gate boolean expression is the foundational architecture for several critical hardware subsystems:
- Parity Generators and Checkers: In ECC (Error-Correcting Code) RAM and serial communication protocols, EX-NOR trees are used to verify if the number of HIGH bits matches the expected even or odd parity. If a single bit flips due to cosmic radiation or crosstalk, the EX-NOR parity checker flags a hardware interrupt.
- Phase Detectors in PLLs: A Type-I Phase-Locked Loop uses an XOR or EX-NOR gate as a phase detector. When comparing a reference clock to a VCO (Voltage-Controlled Oscillator) feedback clock, the EX-NOR output yields a duty cycle proportional to the phase difference between the two signals, which is then filtered into a DC tuning voltage.
- Address Decoding: In legacy memory architectures, banks of EX-NOR gates compare the CPU address bus against hardware jumper pins to assert a chip-select (CS) line only when the addresses perfectly match.
Be aware that the popular 74HC266 features open-drain outputs, not standard push-pull outputs. This means the IC can pull the output line LOW, but it cannot drive it HIGH. You must install an external pull-up resistor (typically 4.7kΩ to 10kΩ) to V_CC on the output pin, or your logic analyzer will only ever read floating LOW states. This architecture is specifically designed to allow wire-ANDing multiple outputs together without short-circuiting the silicon.
Frequently Asked Questions
How do you write the EX-NOR gate boolean expression for three inputs?
This is a massive trap for hobbyists. A 3-input XNOR gate (Y = A ⊙ B ⊙ C) does not output HIGH when all three inputs are identical. Because XNOR is just an inverted XOR, a 3-input XNOR acts as an 'even parity' checker. If A=1, B=1, and C=1, the internal XOR evaluates to 1, meaning the inverted XNOR output is 0. If you actually need a 3-input 'equality detector' (output HIGH only if A=B=C), you cannot use a single 3-input XNOR expression. You must use the expression: Y = (A ⊙ B) · (B ⊙ C), which requires two 2-input EX-NOR gates and one AND gate.
What is the exact difference between the EX-NOR and XOR boolean expressions?
The XOR (Exclusive-OR) expression is Y = A'B + AB'. It outputs HIGH only when the inputs are different (one is 0, the other is 1). The EX-NOR expression is Y = AB + A'B'. It outputs HIGH only when the inputs are the same (both 0 or both 1). In physical silicon, an EX-NOR gate is literally an XOR gate with a NOT gate (inverter) attached to the output pin. In FPGA Verilog/VHDL code, XOR is represented by the caret (^) symbol, while EX-NOR is represented by the tilde-caret (~^) symbol.
Can I build an EX-NOR gate using only NAND gates?
Yes, you can construct a fully functional 2-input EX-NOR gate using exactly five 2-input NAND gates (such as those found in a 74HC00 IC). You use two NAND gates to create the inverted inputs (A' and B'), two more NAND gates to create the AND equivalents of the minterms, and a final NAND gate configured as an OR-equivalent to sum them. This is a common exercise in digital logic courses to prove 'NAND completeness,' but on a real PCB, it wastes board space and increases propagation delay. Always use a dedicated 74HC266 or 74LS266 IC unless you are specifically constrained by parts shortages or discrete transistor design.
