Dropout voltage ($V_{DO}$) is the minimum voltage difference between input and output required for a linear regulator to maintain its target output. If your 5V USB line sags to 4.6V under load and your regulator has a 1.5V dropout, your 3.3V rail will collapse to 3.1V, triggering a brownout reset on your microcontroller. Selecting the right dropout voltage regulator is not about picking the part with the lowest quiescent current; it is about calculating worst-case headroom, thermal dissipation, and output noise to ensure your load never starves.
What is Dropout Voltage and Why It Dictates Your Topology
The dropout voltage is fundamentally determined by the pass element architecture inside the linear regulator. When the input voltage drops too close to the output voltage, the pass transistor exits its active/saturation region and enters the ohmic (triode) region, acting like a simple resistor rather than a controlled current source. At this point, the output voltage tracks the input voltage minus the resistive drop.
Understanding the pass element topology explains why older parts fail in low-headroom scenarios:
- NPN Darlington (e.g., LM317): Requires two base-emitter junction drops plus collector-emitter saturation. Typical $V_{DO}$ is 1.5V to 2.5V. Useless for 5V-to-3.3V conversion if the 5V rail has any sag.
- PNP Pass Transistor (e.g., LM2940): Requires only one $V_{CE(sat)}$ drop. Typical $V_{DO}$ is 0.4V to 0.6V. Better, but still marginal for battery-powered 3.3V systems as the cell discharges.
- PMOS Pass Transistor (e.g., AP2112, TPS7A47): The dropout is simply the load current multiplied by the $R_{DS(on)}$ of the PMOS FET. Typical $V_{DO}$ is 100mV to 300mV. This is the architecture used in modern Low Dropout (LDO) regulators.
Linear LDO vs. Switching Buck: The Heat and Noise Trade-off
When your input-to-output differential is large, the dropout voltage spec matters less than thermal limits. Linear regulators burn the excess voltage as heat, while switching buck converters store and transfer energy via an inductor. Here is how the two topologies compare for a standard 12V-to-3.3V, 500mA load.
| Criterion | Linear LDO (e.g., AP2112) | Switching Buck (e.g., TPS563201) |
|---|---|---|
| Efficiency | 27.5% ($V_{OUT} / V_{IN}$) | 85% - 92% |
| Heat Dissipation ($P_D$) | 4.35W (Requires massive heatsink) | ~0.6W (Handled by PCB copper pour) |
| Output Noise / Ripple | < 60µV RMS (Ultra-clean) | 10mV - 30mV p-p (Switching ripple) |
| Quiescent Current ($I_Q$) | 50µA - 1mA | 50µA - 5mA (Depends on PWM/PFM mode) |
| External Components | 2 Ceramic Capacitors | Inductor, Schottky/Sync FET, 3 Caps, Bootstrap Cap |
| Cost (1k qty) | $0.10 - $0.25 | $0.60 - $1.20 (incl. inductor) |
The Verdict: Use a linear LDO when the voltage drop is small (e.g., 5V to 3.3V) or when powering noise-sensitive analog front-ends (ADCs, RF transceivers, audio DACs). Use a switching buck converter when the input voltage is more than 2V above the output, or when the load current exceeds 300mA on a high-differential rail.
Design Example: 5V to 3.3V at 500mA for an ESP32
Let us design a 3.3V rail for an ESP32-WROOM-32 module powered by a standard 5V USB line. The ESP32 draws baseline currents around 80mA but spikes to 450mA during WiFi transmission bursts.
1. Specifications and Part Selection
- Input Range: 4.5V to 5.5V (accounting for USB cable voltage drop).
- Output Target: 3.3V ±2%.
- Max Load: 500mA.
- Selected Part: Diodes Inc. AP2112K-3.3 (SOT-25 package). It features a 250mV max dropout at 600mA and 75dB PSRR at 1kHz.
2. Headroom Verification
At 500mA, the AP2112K-3.3 has a typical dropout of 200mV. Worst-case input = 4.5V. Available headroom = 4.5V - 3.3V = 1.2V. Since 1.2V > 0.2V, the regulator will easily maintain regulation during USB sag.
3. Thermal and Derating Math
Power dissipated in the LDO is calculated as: $P_D = (V_{IN(max)} - V_{OUT}) \times I_{OUT} + (V_{IN(max)} \times I_Q)$
Ignoring the microamp-level $I_Q$: $P_D = (5.5V - 3.3V) \times 0.5A = 1.1W$
Input Protection and Ripple Expectations
A regulator is only as stable as the input feeding it and the capacitors buffering it. Modern PMOS LDOs like the AP2112 or TI's TPS7A series are designed specifically for low-ESR Multi-Layer Ceramic Capacitors (MLCCs). Older PNP designs required high-ESR tantalum capacitors to maintain control loop stability; using ceramics with them causes high-frequency oscillation.
Capacitor Selection
- Input Cap: 10µF X7R MLCC (0805 size). Placed within 2mm of the $V_{IN}$ pin to provide a low-impedance local energy reservoir for transient load spikes.
- Output Cap: 22µF X7R MLCC. The higher capacitance improves transient response when the ESP32 wakes its RF radio, preventing the output from dipping below the 3.14V brownout threshold.
Ripple and PSRR
Power Supply Rejection Ratio (PSRR) defines how well the LDO blocks input ripple from reaching the output. If your 5V input has 50mV of 120Hz ripple from a cheap wall adapter, an LDO with 60dB PSRR at 120Hz will attenuate that ripple by a factor of 1000, leaving just 50µV on the 3.3V rail. However, PSRR degrades at higher frequencies. If you are cascading an LDO after a switching buck converter running at 1.5MHz, check the LDO datasheet's PSRR graph at 1.5MHz. Many standard LDOs drop to 20dB (10x attenuation) at RF frequencies, meaning switching noise will still bleed through to sensitive analog pins.
Input Protection
If the device is user-facing, add a P-channel MOSFET (e.g., SI2301) for reverse-polarity protection. Unlike a series diode which wastes 0.4V of precious headroom, a P-FET drops only millivolts ($I \times R_{DS(on)}$), preserving your dropout margin.
The Regulator Decision Tree: Pick Your Part
Stop guessing and use this decision matrix to select the exact topology and part number for your next schematic. This framework assumes a standard commercial temperature range (0°C to 70°C) and FR4 PCB construction.
| Condition / Constraint | Topology Choice | Concrete Part Pick |
|---|---|---|
| $V_{IN} - V_{OUT} < 1.5V$ AND $I_{LOAD} < 250mA$ | Standard Ultra-Low $I_Q$ LDO | Microchip MCP1700-33 (SOT-23, 250mA, 175mV dropout, 1.6µA $I_Q$) |
| $V_{IN} - V_{OUT} < 2.0V$ AND $I_{LOAD} > 250mA$ (e.g., 5V to 3.3V MCU) | High-Current PMOS LDO | Diodes AP2112K-3.3 (SOT-223, 600mA, 250mV dropout, low cost) |
| $V_{IN} - V_{OUT} > 2.5V$ AND $I_{LOAD} > 300mA$ | Synchronous Switching Buck | TI TPS563201 (SOT-23-6, 3A, 95% eff, integrated FETs) |
| Load is a 16-bit+ ADC, RF Synth, or Audio DAC (Noise < 10µV) | Ultra-High PSRR / Low-Noise LDO | TI TPS7A47 (Programmable, 1A, 4.4µV RMS noise, 72dB PSRR at 1MHz) |
| Battery powered, $V_{IN}$ crosses $V_{OUT}$ as it dies (e.g., 1S LiPo to 3.3V) | Buck-Boost or Ultra-Low Dropout LDO | TI TPS63000 (Buck-Boost) OR TLV75733P (LDO, 250mV drop, but output sags at end of battery life) |
For the vast majority of bench prototypes, IoT nodes, and hobbyist microcontroller builds stepping down a 5V USB rail to 3.3V at currents under 600mA, the AP2112K-3.3 in a SOT-223 package is the definitive default choice. It provides the necessary 250mV dropout headroom to survive USB cable sag, handles the thermal load of a 500mA ESP32 burst without triggering thermal shutdown, and costs pennies. If your input voltage exceeds 7V or your load exceeds 1A, abandon the linear topology entirely and route the board for a TPS563201 switching buck to prevent melting your PCB.
For deeper analysis on loop stability and capacitor ESR requirements, refer to the Low Dropout Regulator Basics guide on All About Circuits and the Texas Instruments LDO Design Overview.
