The distributive law in Boolean algebra states that a logical operation (AND or OR) can be distributed across another operation inside parentheses, allowing you to expand or factor logic expressions just like multiplying a number across a sum in standard arithmetic. While this sounds like pure math, on the workbench or in a control panel, applying this law dictates how many relay poles you need to buy, how your PLC ladder logic is structured, and whether your 24VDC contactor coils receive enough voltage to pull in reliably.
The Two Forms of the Distributive Law (With Numeric Examples)
In digital logic and relay circuits, we deal with two distinct forms of the distributive law. The first behaves exactly like standard algebra, while the second is unique to Boolean math and frequently trips up technicians transitioning from standard electrical math.
Form 1: AND distributing over OR
This is the familiar form: A · (B + C) = (A · B) + (A · C). If you have a master enable switch (A) that must be ON for either of two parallel sensors (B or C) to trigger an output, you can wire it as one AND gate feeding an OR gate, or two AND gates feeding an OR gate.
Form 2: OR distributing over AND
This is the Boolean-exclusive form: A + (B · C) = (A + B) · (A + C). In standard algebra, you cannot factor A + BC this way. In Boolean logic, you can.
- Left Side: A + (B · C) → 1 + (0 · 1) → 1 + 0 = 1 (True)
- Right Side: (A + B) · (A + C) → (1 + 0) · (1 + 1) → 1 · 1 = 1 (True)
Where You Meet This in Practice
What the distributive law changes in a real circuit is your physical wiring topology and your Bill of Materials (BOM). You will encounter this when:
- Optimizing Relay Panels: You are out of DPDT (Double Pole Double Throw) relays but have plenty of SPDTs. Factoring an expression using the distributive law can reduce the total number of series/parallel contacts required, saving physical panel space.
- PLC Ladder Logic Scan Times: In a Siemens S7-1200 or Allen-Bradley CompactLogix, expanding a factored rung into its distributed form can sometimes parallelize logic branches, marginally reducing scan time in massive programs, though modern compilers often handle this optimization automatically.
- FPGA and CPLD Routing: When programming an ESP32's internal logic or configuring a Xilinx FPGA, the synthesis tool uses the distributive law to map your logic into Look-Up Tables (LUTs). Factoring reduces the number of LUTs consumed.
The most common practical application is factoring to save relay contacts. If your logic requires (A · B) + (A · C), you are using two contacts for A. By factoring it to A · (B + C), you only need one physical contact for A, placed before the parallel B/C branch.
Real-World Scenario Walkthrough: CNC Exhaust Fan Interlock
To understand how misapplying this law destroys hardware, let's look at a hardwired 24VDC relay logic circuit for an industrial exhaust fan.
The Setup: The fan must turn ON if the Fire Alarm triggers (A), OR if both the Manual Override Switch (B) AND the Room Occupancy Sensor (C) are active. The Boolean equation is: Fan = A + (B · C).
The Numbers: The control circuit uses 24VDC solid-state relays (SSRs) for the logic gates to avoid mechanical contact bounce. The main exhaust fan contactor coil requires a minimum of 19.2V (80% of nominal) to pull in reliably and draws 1.5A on inrush.
The Outcome: A junior technician wanted to use standard, identical DPDT relay modules for the whole board. To make the wiring symmetrical, they applied the second distributive law, converting the logic to (A + B) · (A + C). They wired two parallel branches (A||B and A||C) in series. Logically, the circuit worked perfectly on the bench with a multimeter.
What Went Wrong: The tech forgot that solid-state relays have a forward voltage drop. Each SSR in the path dropped about 1.5V. Because the new topology required the current to pass through four SSRs in series (two in the top branch, two in the bottom branch), the total voltage drop was 6V. When the contactor tried to pull in, the voltage at the coil was 18V (75% of nominal). The contactor chattered violently, arced, and welded its main power contacts shut. The fan ran continuously until the main breaker was manually thrown.
Common Confusions: Boolean vs. Standard Algebra
The most frequent mistake makers and students make is assuming standard algebraic rules apply to logic circuits. The distributive law is where this assumption causes the most damage. Below is a comparison of how the two systems handle distribution and factoring.
| Operation | Standard Algebra (Numbers) | Boolean Algebra (Logic 1/0) | Physical Circuit Equivalent |
|---|---|---|---|
| Distribution | A(B + C) = AB + AC | A · (B + C) = (A · B) + (A · C) | Series contact feeding two parallel branches |
| Reverse Factoring | A + BC ≠ (A+B)(A+C) | A + (B · C) = (A + B) · (A + C) | Two parallel blocks wired in series |
| Absorption | A + AB ≠ A | A + (A · B) = A | A bypass switch wired in parallel with a series branch |
| Idempotent Law | A + A = 2A | A + A = A | Two identical switches in parallel act as one switch |
For a deeper dive into how these rules map to physical gates, the Boolean Algebra Laws guide on Electronics Tutorials provides excellent truth-table proofs for every variation.
FAQ: Distributive Law in Logic Design
Does the distributive law apply to XOR (Exclusive-OR) gates?
No. The distributive law only works cleanly with standard AND and OR operations. XOR does not distribute over AND, nor does AND distribute over XOR in a way that simplifies standard relay wiring. If your logic requires an XOR, you must use dedicated XOR ICs (like the 74HC86) or build it from a specific NAND/NOR gate arrangement; you cannot simplify it using the distributive law.
How does factoring with the distributive law affect PLC scan time?
In a PLC, a factored expression like A AND (B OR C) requires the processor to evaluate B and C, OR them, and then AND the result with A. The expanded form (A AND B) OR (A AND C) requires evaluating A twice. While modern PLCs scan in microseconds and the difference is negligible for a single rung, in a massive program with thousands of rungs, factoring reduces the total number of logic instructions, slightly decreasing the overall scan cycle time and freeing up memory.
Can I use the distributive law to simplify a circuit with NOT (inversion) gates?
Yes, but you must combine it with De Morgan's Theorems first. If you have an expression like A · (B' + C'), you cannot distribute it directly without altering the inversions. You would typically apply De Morgan's to the inner terms first, converting the OR of inverted inputs into an AND of non-inverted inputs, and then apply the distributive law. For standard logic gate mapping, refer to the Boolean Rules chapter in the All About Circuits digital textbook for step-by-step simplification examples.
