An XOR (Exclusive OR) gate outputs a HIGH logic level only when its inputs differ. While you can buy a 74HC86 integrated circuit for under $0.50, designing a discrete xor gate circuit diagram from individual transistors reveals the underlying current-steering mechanics of digital logic. The most robust discrete topology avoids the voltage degradation of bipolar resistor-transistor logic (RTL) and instead uses a 4-transistor CMOS pass-gate multiplexer. This guide details the exact node labels, component values, and failure modes required to build and test this circuit on a breadboard.
The 4-Transistor CMOS Pass-Gate Topology & Node Labels
The internal silicon architecture of a standard 74HC86 XOR gate relies on transmission gates (pass-transistors). To replicate this discretely, we use a 4-transistor multiplexer core that routes either the true or inverted input to the output based on the state of the second input.
Core Components: Two N-channel MOSFETs (2N7000) and two P-channel MOSFETs (BS250).
- Node A: Primary data input.
- Node A_INV: Inverted data input (generated by a standard CMOS inverter).
- Node B: Select input.
- Node B_INV: Inverted select input (generated by a second CMOS inverter).
- Node Y: Final output.
Topology Routing
The circuit functions as a 2-to-1 multiplexer where the output logic is defined by the equation: Y = (B AND A) OR (B_INV AND A_INV).
- Transmission Gate 1 (Passes A when B=1):
- M1 (2N7000 NMOS): Gate = Node B, Drain = Node A, Source = Node Y.
- M2 (BS250 PMOS): Gate = Node B_INV, Drain = Node A, Source = Node Y.
- Transmission Gate 2 (Passes A_INV when B=0):
- M3 (2N7000 NMOS): Gate = Node B_INV, Drain = Node A_INV, Source = Node Y.
- M4 (BS250 PMOS): Gate = Node B, Drain = Node A_INV, Source = Node Y.
Why this topology over RTL?
A traditional series/parallel BJT (2N3904) RTL XOR suffers from severe voltage degradation. Each BJT base-emitter junction drops ~0.7V, meaning a 5V input degrades to 3.6V after one stage, destroying noise margins. The CMOS pass-gate topology routes the signal directly through the drain-source channel, maintaining full 0V to 5V rail-to-rail swing with zero static power draw.
Behavior Table & Failure Mode Contrast
Understanding how the circuit reacts to input changes—and what happens when a component fails—is critical for bench debugging. Below is the truth table mapped to the physical transistor states.
| Node A | Node B | Active Path | Passed Signal | Node Y (Output) |
|---|---|---|---|---|
| 0 (LOW) | 0 (LOW) | M3 & M4 (TG2) | A_INV (HIGH) | 1 (HIGH) |
| 0 (LOW) | 1 (HIGH) | M1 & M2 (TG1) | A (LOW) | 0 (LOW) |
| 1 (HIGH) | 0 (LOW) | M3 & M4 (TG2) | A_INV (LOW) | 1 (HIGH) |
| 1 (HIGH) | 1 (HIGH) | M1 & M2 (TG1) | A (HIGH) | 0 (LOW) |
What Breaks at the Extremes?
When building discrete logic, component faults behave differently than in silicon. Here is the failure-mode contrast between this CMOS MUX and a standard series/parallel BJT network:
- Short Circuit (M1 Drain-to-Source): If M1 shorts internally, Node A constantly bleeds to Node Y regardless of Node B. If B=0 and A=1, M1 fights the active TG2 path, causing a direct VCC-to-GND short through the input inverters. Contrast with BJT RTL: A shorted BJT in an RTL network typically just pulls the output permanently HIGH or LOW without creating a destructive low-impedance short across the power rails.
- Open Circuit (M4 Source-to-Drain): If the PMOS M4 fails open, TG2 loses its ability to pass a strong HIGH signal. When B=0 and A=0, the circuit attempts to pass A_INV (HIGH) to Y. The NMOS M3 remains active, but NMOS transistors pass a "weak 1" (VCC minus the threshold voltage, roughly 3.0V). The output will read as a degraded HIGH, highly susceptible to breadboard noise. Contrast with BJT RTL: An open BJT in a pull-up network simply leaves the output floating, requiring an external pull-up resistor to define the state.
Design Walkthrough: Picking Real Component Values
To build this xor gate circuit diagram on a breadboard, you must account for parasitic capacitance and gate threshold voltages. We assume a 5V logic supply and a 25°C ambient environment.
- The Inverters (Generating A_INV and B_INV): Each inverter requires one 2N7000 (NMOS) and one BS250 (PMOS). Tie the gates together as the input, and the drains together as the output. Connect the BS250 source to 5V and the 2N7000 source to GND.
- Gate Resistors (R1-R4): Place a 10kΩ series resistor on every gate input (Nodes A, B, and the inverter inputs). Breadboard wires act as antennas; without 10kΩ dampening, high-frequency ringing will cause the MOSFETs to oscillate in their linear region, generating heat and erratic outputs.
- Output Pull-Down (R5): Place a 100kΩ resistor between Node Y and GND. During the nanosecond dead-time when TG1 turns off and TG2 turns on, Node Y is momentarily high-impedance. The 100kΩ resistor prevents the output from floating and triggering false logic transitions in downstream circuits.
- Input Protection: MOSFET gates are highly sensitive to electrostatic discharge (ESD). While the 2N7000 has internal Zener diodes, always touch a grounded surface before handling the BS250 PMOS transistors, which are notoriously ESD-fragile.
For a comprehensive look at how these discrete transmission gates scale into commercial silicon, refer to the Texas Instruments SN74HC86 Datasheet, which details the exact propagation delays and drive currents of the integrated equivalent.
Step-by-Step Breadboard Testing Procedure
Do not apply power until the wiring is verified. MOSFETs will latch up if inputs are left floating during power-up.
- De-energize and Prep: Ensure the breadboard power supply is OFF. Connect the 5V and GND rails across the top and bottom bus strips.
- Place the Inverters: Insert two 2N7000s and two BS250s to form the A_INV and B_INV generators. Verify continuity from the PMOS sources to the 5V rail and NMOS sources to GND.
- Wire the MUX Core: Insert the remaining four transistors (M1-M4). Wire the drains and sources to form the two transmission gates as defined in the topology section.
- Install Input Switches: Connect SPDT toggle switches or a DIP switch to Nodes A and B. Critical: Wire 10kΩ pull-down resistors from the switch outputs to GND to ensure a solid LOW state when the switch is open.
- Verify Dead State: Turn on the 5V supply. With both switches LOW (A=0, B=0), use a multimeter to measure the voltage at Node Y. It should read >4.5V (HIGH).
- Measure Static Current: Break the 5V rail connection and insert your multimeter in series (ammeter mode). A properly functioning CMOS XOR should draw less than 10 µA of static current. If you read >1 mA, you have a floating gate or a shorted transmission gate.
- Dynamic Test: Toggle the switches through all four states (00, 01, 10, 11) and verify the output LED or multimeter reading matches the XOR truth table.
Frequently Asked Questions
How do I make an XOR gate circuit diagram using only NAND gates?
If you lack discrete MOSFETs but have a 74HC00 (Quad NAND) IC, you can build an XOR gate using four NAND gates. The logic equation is Y = (A NAND (A NAND B)) NAND (B NAND (A NAND B)). Gate 1 takes A and B. Gate 2 takes A and the output of Gate 1. Gate 3 takes B and the output of Gate 1. Gate 4 takes the outputs of Gates 2 and 3. This requires 4 transistors per NAND gate, totaling 16 transistors internally—much less efficient than the 4-transistor pass-gate MUX, but easier to wire if you only have ICs.
Why does my discrete XOR gate output float when both inputs are LOW?
If you are using a BJT (2N3904) RTL topology instead of the CMOS pass-gate described above, the output will float when both inputs are LOW because neither the pull-up nor the pull-down network is fully saturated. RTL gates require a dedicated pull-down resistor (typically 10kΩ) on the output node to define the LOW state. The CMOS topology avoids this by always providing a low-impedance path to either VCC or GND via the transmission gates.
Can I use an XOR gate as a phase detector in a PLL circuit?
Yes. An XOR gate is the classic "Type I" phase detector in Phase-Locked Loops (PLLs). When two square waves of the same frequency but different phases are fed into Nodes A and B, the output at Node Y produces a pulse train whose duty cycle is directly proportional to the phase difference. A low-pass filter on Node Y converts this duty cycle into a DC error voltage. For deep-dive theory on this application, All About Circuits provides excellent foundational material on CMOS logic switching characteristics.
What is the propagation delay difference between a 74HC86 and a discrete MOSFET XOR?
A commercial 74HC86 IC has a typical propagation delay of about 10 ns at 5V. Your discrete breadboard version using 2N7000 and BS250 transistors will exhibit delays between 50 ns and 150 ns. This is due to the high parasitic capacitance of breadboard contacts (roughly 2-5 pF per node) combined with the relatively high on-resistance (Rds_on) of the discrete MOSFETs (approx. 5Ω for the 2N7000). This limits the maximum reliable clock frequency of the discrete XOR to roughly 5-10 MHz, compared to the 50+ MHz capability of the integrated IC.
