The fundamental SR (Set-Reset) latch circuit diagram relies on cross-coupled feedback to maintain a bistable state, acting as a basic 1-bit memory element. For a 5V logic system, the most robust integrated implementation uses a 74HC00 quad NAND gate IC, while the educational discrete equivalent uses two 2N3904 NPN transistors with 1kΩ collector and 10kΩ base resistors. Understanding the discrete topology exposes the raw physics of the feedback loop before you abstract it away into logic gates.
The Core Topology and Node Behavior
A discrete SR latch consists of two identical common-emitter amplifier stages where the collector of each transistor feeds the base of the other. This cross-coupling creates a regenerative feedback loop. When Q1 is conducting (saturated), its collector voltage drops to roughly 0.2V, which is insufficient to forward-bias the base-emitter junction of Q2. Consequently, Q2 is cut off, allowing its collector to pull up to VCC. This state is stable indefinitely until an external trigger forces a change.
Below is the behavior table for an active-high discrete BJT SR latch operating at 5V. This table maps the logical inputs to the physical node voltages you should measure with a multimeter on your bench.
| Set (S) Input | Reset (R) Input | Q1 State | Q2 State | Q Output (Q2 Coll.) | Q' Output (Q1 Coll.) | Logical State |
|---|---|---|---|---|---|---|
| LOW (0V) | LOW (0V) | Depends on history | Depends on history | ~5.0V or ~0.2V | ~0.2V or ~5.0V | Hold (Memory) |
| HIGH (5V) | LOW (0V) | Saturated (ON) | Cut-off (OFF) | ~5.0V | ~0.2V | Set (Q=1) |
| LOW (0V) | HIGH (5V) | Cut-off (OFF) | Saturated (ON) | ~0.2V | ~5.0V | Reset (Q=0) |
| HIGH (5V) | HIGH (5V) | Saturated (ON) | Saturated (ON) | ~0.2V | ~0.2V | Invalid / Forbidden |
Component Selection and Design Walkthrough
Designing a reliable discrete SR latch circuit diagram requires calculating resistor values to guarantee deep saturation without exceeding the maximum base current ratings of the transistors. We will use standard 2N3904 NPN transistors, which have a minimum DC current gain (hFE) of 100 and a maximum collector current rating of 200mA.
1. Sizing the Collector Resistors (Rc1, Rc2)
The collector resistors act as pull-ups and limit the current flowing through the transistor when it is saturated. We want a manageable current that is easy to measure but low enough to minimize power dissipation. Let's target a collector current (Ic) of roughly 5mA.
- Formula: Rc = (VCC - VCE(sat)) / Ic
- Calculation: (5V - 0.2V) / 5mA = 960Ω
- Selected Value: 1kΩ (Standard E12 value, yields Ic ≈ 4.8mA)
2. Sizing the Base Resistors (Rb1, Rb2)
To ensure the transistor acts as a closed switch (saturation), we must supply enough base current (Ib) to overcome the hFE. A standard engineering rule of thumb is to design for a forced beta (β_forced) of 10 to 20, meaning we supply 5 to 10 times more base current than strictly required by the hFE.
- Target Ib: Ic / β_forced = 4.8mA / 10 = 0.48mA
- Formula: Rb = (VCC - VBE) / Ib
- Calculation: (5V - 0.7V) / 0.48mA = 8,958Ω
- Selected Value: 10kΩ (Standard E12 value, yields Ib ≈ 0.43mA)
With an actual Ib of 0.43mA and an Ic of 4.8mA, our forced beta is 11.1. Because 11.1 is significantly lower than the 2N3904's minimum hFE of 100, the transistor is driven deep into saturation, guaranteeing a VCE(sat) of roughly 0.2V. This ensures a clean, unambiguous LOW signal to the base of the cross-coupled transistor.
Step-by-Step Breadboard Testing
Translating the schematic to a physical breadboard requires careful attention to node routing. Cross-coupled circuits are prone to parasitic oscillation if wires are too long, so keep your jumper leads short and tight.
- Place the Transistors: Insert two 2N3904 transistors into the breadboard, leaving at least three empty rows between them to prevent accidental shorting. Identify the emitter, base, and collector (flat side facing you, pins are E, B, C from left to right).
- Establish Ground: Wire both emitters directly to the common ground rail. Do not share a long daisy-chained ground path; use a star ground or direct rail connections to prevent ground bounce from triggering false state changes.
- Install Collector Pull-ups: Insert a 1kΩ resistor from the VCC (5V) rail to the collector of Q1. Repeat for Q2. These are your Q' and Q output nodes, respectively.
- Wire the Cross-Coupling: Connect a 10kΩ resistor from the collector of Q1 to the base of Q2. Connect a second 10kΩ resistor from the collector of Q2 to the base of Q1. This is the regenerative feedback loop.
- Add Input Steering: To control the latch, connect a 10kΩ resistor from your 'Set' switch (or jumper) to the base of Q1. Connect another 10kΩ resistor from your 'Reset' switch to the base of Q2. Add 10kΩ pulldown resistors from each base to ground to ensure the inputs default to LOW when the switches are open.
- Verify Before Powering: Use your multimeter in continuity mode to check for shorts between VCC and GND. A shorted breadboard contact will fry your power supply or USB port.
- Power and Test: Apply 5V. Measure the collector voltages. One should read ~5.0V and the other ~0.2V. Momentarily touch the Set input to 5V; the states should flip. Remove the input, and the latch must hold its new state.
Failure Modes: What Breaks at the Extremes?
Understanding how an SR latch circuit diagram fails when components degrade or break is critical for troubleshooting. Here is the failure-mode contrast for the discrete BJT topology.
| Component | Failure Type | Circuit Behavior | Diagnostic Measurement |
|---|---|---|---|
| Base Resistor (Rb) | Open Circuit | The associated transistor can never turn ON. The latch permanently locks in the opposite state, ignoring one of the inputs. | Base voltage reads 0V regardless of input switching. |
| Collector Resistor (Rc) | Short Circuit | VCC is applied directly to the cross-coupled base resistor. Base current spikes to ~0.5mA (safe for 2N3904), but the output node is stuck HIGH. | Collector node reads a hard 5.0V; transistor gets warm. |
| Transistor (BJT) | Collector-Emitter Short | The collector is pulled permanently to ground. The cross-coupled transistor receives 0V at its base and remains permanently cut off. | VCE measures 0.0V; opposite collector measures 5.0V. |
| Cross-Coupling Resistor | Open Circuit | Feedback is broken. The circuit ceases to be a latch and acts as two independent, non-inverting switches that do not hold state. | Removing an input immediately causes the output to float or drop. |
NAND vs. NOR: Why Choose This Topology?
When moving from discrete transistors to integrated logic gates, you must choose between a NAND-based SR latch (active-low inputs) and a NOR-based SR latch (active-high inputs). While the discrete circuit above mimics the active-high behavior of a NOR latch, the NAND topology is vastly more common in modern digital design.
NAND Latch (74HC00)
- Inputs: Active-LOW (S', R')
- Idle State: Both inputs HIGH
- Advantage: Pulling a line to ground via a switch or open-drain transistor is electrically simpler and more noise-immune than driving it to VCC.
- IC Availability: Quad NAND gates are the most ubiquitous and cheapest logic ICs in existence.
NOR Latch (74HC02)
- Inputs: Active-HIGH (S, R)
- Idle State: Both inputs LOW
- Advantage: More intuitive for beginners; pressing a button to VCC directly 'Sets' or 'Resets' the latch.
- Drawback: Requires pull-down resistors on inputs to prevent floating nodes, adding component count.
For a breadboard project where you are triggering the latch with a simple tactile switch, the NAND latch is the superior choice. You wire one side of the switch to ground and the other to the input pin, relying on the internal or external pull-up resistor to keep the line HIGH. Pressing the switch pulls the input LOW, triggering the Set or Reset action without needing external pull-down resistors or risking a dead short if a switch fails.
For deeper reading on logic gate propagation delays and metastability in latches, refer to the Texas Instruments SN74HC00 Datasheet and the foundational breakdown of sequential logic at Electronics Tutorials.
