A NOR gate outputs a logic HIGH only when all of its inputs are LOW. If any input goes HIGH, the output immediately pulls LOW. While you can buy a quad 2-input NOR IC like the 74HC02 or CD4001 for pennies, understanding how to draft and build a discrete NOR gate circuit diagram using Resistor-Transistor Logic (RTL) is a foundational exercise in digital design. It forces you to confront the physical realities of logic levels, saturation voltages, and fan-out limitations that abstract logic symbols hide.
In this guide, we will design a 2-input discrete RTL NOR gate from scratch, select exact component values for a 5V logic system, analyze extreme failure modes, and walk through a step-by-step breadboard verification process.
The Discrete RTL NOR Gate Topology and Node Map
Resistor-Transistor Logic (RTL) uses resistors for the input network and bipolar junction transistors (BJTs) as the switching elements. For a NOR gate, the RTL topology is exceptionally elegant because it places the transistors in parallel. This contrasts with Diode-Transistor Logic (DTL), which uses series diodes and is naturally better suited for NAND gates.
Node Labels and Topology Description
To build this circuit, we define five primary nodes:
- VCC: The positive supply rail (5.0V DC).
- GND: The common ground reference (0V).
- Node A (Input 1): Connects to the base of Q1 through resistor R1.
- Node B (Input 2): Connects to the base of Q2 through resistor R2.
- Node Y (Output): The shared collector node of Q1 and Q2, pulled up to VCC via R3.
When both Node A and Node B are at 0V (LOW), both transistors are in cutoff. No current flows through the collector-emitter junctions, and Node Y is pulled up to VCC (HIGH) through R3. If either Node A or Node B receives 5V (HIGH), the corresponding transistor saturates, creating a low-resistance path from Node Y to GND, pulling the output LOW.
Design Walkthrough: Picking Real Component Values
Abstract schematics are useless without real part numbers and calculated values. For a 5V logic system, we need to ensure the transistors saturate fully when ON and remain firmly in cutoff when OFF.
Component Selection
- Transistors (Q1, Q2): 2N3904 (General-purpose NPN BJT). According to the ON Semiconductor 2N3904 datasheet, it has a minimum hFE (DC current gain) of 100 at 10mA and a Vce_sat (collector-emitter saturation voltage) of roughly 0.2V.
- Base Resistors (R1, R2): 10kΩ. These limit the base current to prevent damaging the transistor and to keep the input impedance reasonably high.
- Collector Pull-up Resistor (R3): 1kΩ. This pulls the output HIGH and limits the collector current when a transistor saturates.
The Math: Proving Saturation
Assume Node A is HIGH (5V) and Node B is LOW (0V). Q1 turns ON. The base current (Ib) for Q1 is calculated using Ohm's Law, accounting for the base-emitter voltage drop (Vbe ≈ 0.7V):
Ib = (VCC - Vbe) / R1 = (5.0V - 0.7V) / 10,000Ω = 0.43mA
With an hFE of 100, the transistor could theoretically support a collector current (Ic) of 43mA. However, the actual collector current is limited by the pull-up resistor R3 and the load. The maximum Ic through R3 is:
Ic_max = (VCC - Vce_sat) / R3 = (5.0V - 0.2V) / 1,000Ω = 4.8mA
Since the available base current (0.43mA) can drive up to 43mA, but the circuit only demands 4.8mA, Q1 is driven deep into saturation. The output at Node Y will sit comfortably at Vce_sat (≈ 0.2V), which is well below the 0.8V maximum threshold for a logic LOW in standard 5V TTL/CMOS systems.
Behavior Table and Extreme Failure Modes
Understanding a NOR gate circuit diagram requires knowing how it behaves under normal conditions and how it fails when components degrade. Below is the standard truth table followed by a failure-mode contrast matrix.
Standard Logic Behavior
| Input A | Input B | Q1 State | Q2 State | Output Y (Node Y) |
|---|---|---|---|---|
| LOW (0V) | LOW (0V) | Cutoff | Cutoff | HIGH (~5.0V) |
| HIGH (5V) | LOW (0V) | Saturated | Cutoff | LOW (~0.2V) |
| LOW (0V) | HIGH (5V) | Cutoff | Saturated | LOW (~0.2V) |
| HIGH (5V) | HIGH (5V) | Saturated | Saturated | LOW (~0.2V) |
Failure-Mode Contrast: What Breaks at the Extremes?
In physical circuits, components fail open or short. Here is exactly what happens to Node Y when a single element fails.
| Component | Failure Mode | Effect on Output Y |
|---|---|---|
| R1 (Base A) | Open | Input A is ignored. Gate acts as a 1-input inverter for Input B. |
| R1 (Base A) | Short | If Input A goes HIGH, excessive current flows into Q1 base, likely destroying Q1 and pulling the Input A source voltage down. |
| Q1 (Transistor) | C-E Short | Output Y is permanently stuck LOW (~0V), regardless of inputs. |
| Q1 (Transistor) | C-E Open | Input A is ignored. Gate acts as a 1-input inverter for Input B. |
| R3 (Pull-up) | Open | Output Y floats. When both inputs are LOW, a high-impedance multimeter will read erratic voltages (1.2V - 2.5V) due to EMI pickup. |
RTL gates suffer from poor fan-out. Because the pull-up resistor (R3) is relatively high (1kΩ), the output impedance in the HIGH state is high. If you connect this NOR gate to more than two or three standard TTL inputs, the leakage current of the downstream gates will pull Node Y below the 2.0V minimum required for a logic HIGH. For high fan-out, use a CMOS IC like the NXP HEF4001B instead.
Step-by-Step Breadboard Verification
Follow these numbered steps to build and test the circuit safely. Never wire or modify a circuit while it is energized.
- De-energize the Board: Ensure your breadboard power supply is turned off and unplugged. Verify the rails are dead using a multimeter set to DC voltage.
- Place the Transistors: Insert two 2N3904 transistors (Q1, Q2) into the breadboard, ensuring their flat sides face you. The pins from left to right are Emitter (E), Base (B), and Collector (C).
- Wire the Emitters: Connect the Emitter pins of both Q1 and Q2 directly to the ground (GND) rail.
- Install Base Resistors: Insert a 10kΩ resistor (R1) connecting the Base of Q1 to an empty row (Node A). Repeat with a second 10kΩ resistor (R2) for the Base of Q2 (Node B).
- Wire the Collectors and Pull-up: Jumper the Collector pins of Q1 and Q2 together. Insert the 1kΩ pull-up resistor (R3) connecting this shared collector node (Node Y) to the positive (VCC) rail.
- Connect Power: Connect your power supply to the breadboard rails. Set the voltage to exactly 5.0V DC.
- Verify Logic States: Turn on the power. Use jumper wires to connect Node A and Node B to either VCC (HIGH) or GND (LOW). Measure Node Y with your multimeter. You should read ~5.0V when both inputs are grounded, and ~0.2V when either input is tied to 5V.
Discrete RTL vs. Integrated CMOS (CD4001 / 74HC02)
Why build a discrete NOR gate circuit diagram when integrated circuits exist? The choice depends entirely on your application constraints. As noted in standard digital logic references like the All About Circuits Digital Logic textbook, discrete logic is largely educational or used in extreme high-radiation environments where custom ASICs fail, while ICs dominate commercial design.
| Criteria | Discrete RTL (2N3904) | Integrated CMOS (74HC02 / CD4001) |
|---|---|---|
| Component Count | 5 parts per gate | 1 IC contains 4 gates |
| Propagation Delay | Slow (~100ns+ due to BJT storage time) | Fast (~10ns to 20ns) |
| Power Consumption | High (continuous current through R3 when LOW) | Extremely low (only draws current during switching) |
| Fan-Out Capability | Poor (1 to 3 standard loads) | Excellent (10 to 50 standard loads) |
| Best Use Case | Education, repairing legacy 1960s hardware | Modern digital design, microcontrollers, FPGAs |
NOR Gate Circuit Diagram FAQ
How do I wire a NOR gate circuit diagram using only NAND gates?
NAND gates are universal. To build a 2-input NOR gate using only 2-input NAND gates, you need four of them. First, use two NAND gates as inverters by tying their inputs together; connect Input A to the first inverter and Input B to the second. Then, feed the inverted A and inverted B signals into a third NAND gate. Finally, pass the output of that third gate through a fourth NAND gate (configured as an inverter) to get the final NOR output. The Boolean algebra simplifies to: NOT( (NOT A) NAND (NOT B) ) = A NOR B.
Why is my discrete NOR gate circuit diagram outputting a constant HIGH?
If Node Y is stuck at 5.0V regardless of your inputs, the pull-up resistor (R3) is doing its job, but the transistors are failing to pull the node to ground. Check the following: First, verify your input sources are actually providing 5V; a weak microcontroller GPIO pin might only be outputting 2.5V, which isn't enough to overcome the Vbe threshold and drive the 10kΩ base resistor. Second, check for cold solder joints or loose breadboard contacts on the Emitter pins. If the emitter isn't tied to GND, the transistor cannot complete the circuit. Finally, test the transistors with your multimeter's diode mode to ensure the base-collector and base-emitter junctions haven't failed open.
Can I use a NOR gate circuit diagram to build an SR latch?
Yes, the NOR gate is the standard building block for an active-high SR (Set-Reset) latch. You need two identical 2-input NOR gates. Cross-couple them by connecting the output of the first gate to one input of the second gate, and the output of the second gate to one input of the first. The remaining free inputs become your Set (S) and Reset (R) terminals. When S goes HIGH, the first output drops LOW, forcing the second output HIGH (Set state). When R goes HIGH, the process reverses (Reset state). If using discrete RTL, remember the fan-out limitation: the output of one discrete gate must drive the base resistor of the next, which works fine, but keep the wiring short to avoid capacitive coupling and oscillation.
