If you need to build logic gates using transistors, you are wiring them as voltage-controlled switches. For a basic 2-input NAND gate, the safe default parts are 2N7000 N-channel MOSFETs (for NMOS logic) or 2N3904 NPN BJTs (for RTL/DTL). You bias them into either cutoff (logic 0 output) or the ohmic/saturation region (logic 1 output) using pull-up or pull-down resistors.
While 74HC or 4000-series ICs are cheaper and faster, rolling your own discrete logic gates is a critical bench skill. You need it when designing high-voltage interlocks that exceed standard 5V logic tolerances, when building radiation-hardened circuits where commercial silicon fails, or simply to understand the physical layer of digital design. This guide walks through the exact component values, biasing math, and failure modes you will encounter on the workbench.
The Anatomy of a Discrete Logic Switch
Before wiring a gate, you must understand the physical pins and the operating regions of your chosen transistor. In discrete logic, we only care about two states: fully OFF (cutoff) and fully ON (saturation for BJTs, ohmic/linear for MOSFETs). The active/linear region of a BJT is an unwanted transition zone that causes excess heat and undefined logic levels.
For the 2N3904 NPN BJT, with the flat side facing you and leads pointing down: Pin 1 is Emitter (E), Pin 2 is Base (B), Pin 3 is Collector (C).
For the 2N7000 N-Channel MOSFET, flat side facing you, leads down: Pin 1 is Source (S), Pin 2 is Gate (G), Pin 3 is Drain (D).
| Region | BJT (2N3904) State | BJT Typical Values | MOSFET (2N7000) State | MOSFET Typical Values |
|---|---|---|---|---|
| Cutoff | OFF (Logic 1 at collector) | Vbe < 0.5V, Ic ≈ 0mA | OFF (Logic 1 at drain) | Vgs < 2.0V, Id ≈ 0mA |
| Active/Linear | Transition (Avoid!) | Vbe ≈ 0.65V, Vce = 1-3V | Saturation (Avoid!) | Vgs ≈ 2.5V, Vds = 1-3V |
| Saturation/Ohmic | ON (Logic 0 at collector) | Vbe ≈ 0.7V, Vce(sat) < 0.2V | ON (Logic 0 at drain) | Vgs = 5V, Rds(on) ≈ 1.8Ω |
Building a 2-Input NAND Gate: Circuit and Biasing
A NAND gate outputs a logic LOW only when both inputs are HIGH. Using NMOS logic with 2N7000 MOSFETs, we achieve this by placing two transistors in series between the output node and ground. If both gates receive a HIGH signal, the path to ground is completed, pulling the output LOW.
Component Values and Schematic Setup
- Q1, Q2: 2N7000 N-Channel MOSFETs
- R_Pullup: 4.7kΩ resistor (Connects VCC to the Drain of Q1)
- R_Gate1, R_Gate2: 100Ω resistors (Series gate stoppers to prevent high-frequency ringing)
- R_PD1, R_PD2: 10kΩ resistors (Pull-downs from Gate to Source to prevent floating inputs)
- VCC: 5.0V DC
How to Bias and Select for the Job
Selection starts with the threshold voltage, Vgs(th). The 2N7000 has a Vgs(th) between 2.0V and 3.0V. Because our logic HIGH is 5V, we easily exceed the threshold, driving the MOSFET deep into the ohmic region where Rds(on) drops to about 1.8Ω.
Biasing the inputs is where beginners fail. MOSFET gates have extremely high impedance. If you leave an input unconnected (floating), ambient electromagnetic noise will couple into the gate, randomly turning the transistor on and off. The 10kΩ pull-down resistors ensure the gate defaults to 0V (cutoff) when no signal is applied. The 100Ω series gate resistors form a low-pass filter with the gate's parasitic capacitance, killing any high-frequency ringing caused by long breadboard wires.
- Connect the Source pins of Q1 and Q2 directly to the ground rail.
- Connect the Drain of Q2 to the Source of Q1 (this is the series switching path).
- Wire the 4.7kΩ pull-up resistor from the 5V VCC rail to the Drain of Q1. This node is your Logic Output.
- Wire the 10kΩ pull-down resistors from each Gate to Ground.
- Connect your input signals through the 100Ω gate stopper resistors to the Gates of Q1 and Q2.
Bench Scenario: The Slow Rise-Time Disaster
Theory is clean; the workbench is messy. Here is a real-world scenario demonstrating what happens when you ignore parasitic capacitance in discrete logic design.
Setup: I was building a 24V high-side safety interlock for a motor controller. Standard 5V logic ICs couldn't handle the voltage, so I built a discrete 2-input AND gate using 2N3904 BJTs to drive a relay coil. To minimize standby power draw from the 24V rail, I used a massive 100kΩ pull-up resistor on the collector output.
Numbers: The breadboard and the relay coil introduced roughly 60pF of stray parasitic capacitance at the output node. With a 100kΩ resistor, the RC time constant (τ = R × C) was 6 microseconds. To fully charge to a logic HIGH (approx 5τ), it took 30 microseconds.
Outcome: The microcontroller was sending a 50kHz PWM enable signal (20µs period). Because the rise time took 30µs, the output waveform never reached a valid logic HIGH before the next LOW pulse arrived. The signal looked like a jagged sawtooth wave, and the relay chattered violently, eventually welding its contacts.
What Went Wrong: I optimized for static power consumption but ignored dynamic switching speed. The fix was twofold: I dropped the pull-up resistor to 4.7kΩ (reducing the rise time to ~1.4µs) and added a discrete push-pull totem-pole output stage to actively source current to the relay, rather than relying on a passive resistor.
Failure Modes and Multimeter Diagnostics
Discrete transistors fail differently than monolithic ICs. When a custom logic gate misbehaves, you need to know how to test the individual components without desoldering them immediately.
How Discrete Logic Fails
- ESD Gate Punch-Through (MOSFETs): The gate oxide on a 2N7000 is incredibly thin. A static shock from your finger can exceed the ±20V Vgs maximum, punching a microscopic hole in the oxide. The gate then shorts to the source, and the transistor stays permanently OFF.
- Thermal Runaway (BJTs): If a 2N3904 is biased in the active region instead of saturation, it dissipates heavy power (P = Vce × Ic). As the silicon heats up, its Vbe drops, drawing more base current, which creates more heat, until the junction melts and shorts Collector to Emitter.
- Floating Input Oscillation: Not a component failure, but a circuit failure. Unpulled-down gates act as antennas, picking up 50/60Hz mains hum and rapidly toggling the output, causing massive heat dissipation in the pull-up resistors.
How to Test with a Digital Multimeter (DMM)
Set your DMM to Diode Test Mode. This mode applies a small current and measures the forward voltage drop.
Testing a 2N3904 BJT:
- Place the red probe on the Base, black on the Emitter. You should read 0.60V to 0.70V.
- Reverse the probes (black on Base, red on Emitter). It should read "OL" (Open Loop).
- Test Collector to Emitter in both directions. Both should read "OL". If you read a short (0.00V), the junction has melted from thermal runaway.
Testing a 2N7000 MOSFET:
- Measure Gate to Source in both directions. It must read "OL". If you read any continuity or a diode drop, the gate oxide is blown. Throw it away.
- Measure Drain to Source with the red probe on Drain and black on Source. You should read "OL".
- Reverse the probes (red on Source, black on Drain). You will read a diode drop of roughly 0.45V to 0.55V. This is the intrinsic body diode. It is normal and expected.
Safe Default Part Numbers and Sourcing
When designing discrete logic, stick to jellybean parts that are widely available, cheap, and have well-documented datasheets. Avoid high-power switching MOSFETs (like the IRF520) for logic gates; their massive gate capacitance (hundreds of picofarads) will result in unusably slow switching speeds without heavy gate driver ICs.
| Part Number | Type | Max Vds / Vce | Max Id / Ic | Key Logic Spec | Typical Price (2026) |
|---|---|---|---|---|---|
| 2N7000 | N-Channel MOSFET | 60V | 200mA | Vgs(th): 2.0V - 3.0V | $0.05 / ea |
| BS170 | N-Channel MOSFET | 60V | 500mA | Lower Rds(on) than 2N7000 | $0.12 / ea |
| 2N3904 | NPN BJT | 40V | 200mA | hFE: 100 - 300 (Great for RTL) | $0.03 / ea |
| 2N3906 | PNP BJT | 40V | 200mA | Complement to 2N3904 for totem-poles | $0.03 / ea |
For authoritative reference on the switching characteristics of these components, consult the ON Semiconductor 2N7000 Datasheet for exact capacitance and threshold curves. If you are comparing your discrete gate delays against commercial silicon, the Texas Instruments Designing With Logic Guide (SDYA001A) provides excellent baseline data on propagation delays and noise margins in standard logic families. For deeper theory on biasing BJTs as switches, All About Circuits offers a robust breakdown of calculating base current limits to ensure hard saturation.
Building logic gates using transistors bridges the gap between abstract boolean algebra and physical electronics. By respecting parasitic capacitance, properly biasing your inputs, and testing with a DMM before applying power, you can build robust, custom logic interfaces that handle voltages and environments standard ICs simply cannot survive.
