The most robust and universally adopted circuit diagram of gates in modern digital design is the complementary MOS (CMOS) NAND topology. By placing P-channel MOSFETs in parallel and N-channel MOSFETs in series, you achieve full rail-to-rail voltage swings with near-zero static power consumption. While you will typically buy these as integrated circuits like the 74HC00 or CD4011, understanding how to design, build, and test this topology using discrete components on a breadboard is the fastest way to internalize digital logic physics. Below is the complete design walkthrough, failure-mode analysis, and verification sequence for a discrete 2-input CMOS NAND gate.
The Core Topology: CMOS 2-Input NAND Node Map
A 2-input NAND gate requires four transistors: two P-channel MOSFETs (PMOS) forming the pull-up network, and two N-channel MOSFETs (NMOS) forming the pull-down network. Here is the node mapping for the discrete build:
- VDD (Node 1): Positive supply rail (5V to 15V). Connects to the Source terminals of Q1 and Q2.
- GND (Node 2): Ground reference (0V). Connects to the Source terminal of Q4.
- IN_A (Node 3): Input A. Connects to the Gate of Q1 (PMOS) and the Gate of Q3 (NMOS).
- IN_B (Node 4): Input B. Connects to the Gate of Q2 (PMOS) and the Gate of Q4 (NMOS).
- OUT (Node 5): Output. The junction where the Drains of Q1 and Q2 meet the Drain of Q3.
- Mid-Node (Node 6): The internal series junction between the Drain of Q3 and the Source of Q4.
Behavior Matrix and Failure Mode Extremes
Understanding what happens when the circuit operates normally is only half the battle. You must also know what breaks at the extremes. Below is the steady-state behavior matrix, followed by the critical failure modes.
| IN_A | IN_B | Q1 (PMOS) | Q2 (PMOS) | Q3 (NMOS) | Q4 (NMOS) | OUT State |
|---|---|---|---|---|---|---|
| LOW (0V) | LOW (0V) | ON | ON | OFF | OFF | HIGH (VDD) |
| LOW (0V) | HIGH (VDD) | ON | OFF | OFF | ON | HIGH (VDD) |
| HIGH (VDD) | LOW (0V) | OFF | ON | ON | OFF | HIGH (VDD) |
| HIGH (VDD) | HIGH (VDD) | OFF | OFF | ON | ON | LOW (GND) |
What Breaks at the Extremes?
Extreme 1: The Floating Input (Open Circuit)
If you leave IN_A unconnected on a breadboard, the high-impedance gate of the MOSFET acts as an antenna. It will pick up ambient 50/60Hz mains hum, rapidly toggling the transistor between ON and OFF. During the brief transition windows, both the PMOS and NMOS networks conduct simultaneously. This creates a shoot-through (or crowbar) current path directly from VDD to GND. In a discrete build, this will cause the MOSFETs to overheat and fail; in an IC, it causes severe VDD sag and thermal shutdown.
Extreme 2: Output Shorted to GND
If OUT is accidentally shorted to GND, and both inputs are pulled LOW, Q1 and Q2 turn ON hard. Because there is no current-limiting resistor in the pull-up network of a standard CMOS gate, the PMOS transistors will attempt to source infinite current into the short. The silicon will melt or the bond wires will fuse open. Always use current-limiting resistors on output LEDs or ensure your power supply has foldback current limiting.
Why CMOS Over TTL or RTL?
Before CMOS dominated, Resistor-Transistor Logic (RTL) and Transistor-Transistor Logic (TTL, like the 74LS series) were the standards. Here is why the CMOS topology wins for 99% of modern applications:
- Static Power Draw: RTL and TTL require continuous base current to keep bipolar junction transistors (BJTs) in saturation. A standard 74LS00 NAND gate draws roughly 0.8mA per gate just sitting idle. A CMOS NAND gate draws effectively zero static current (only picoamps of subthreshold leakage), drawing power only during the nanosecond it takes to switch states.
- Voltage Scalability: TTL is strictly bound to a 5V ±5% supply. CMOS logic scales beautifully. A CD4000-series CMOS NAND will function identically whether VDD is 3V, 9V, or 15V, making it ideal for battery-powered and automotive applications.
- Fan-Out and Loading: Because CMOS inputs are capacitive (insulated gates) rather than current-driven (BJT bases), a single CMOS output can drive dozens of other CMOS inputs without voltage droop, whereas TTL fan-out is strictly limited by base-current sourcing capabilities.
Design Walkthrough: Sizing and Selecting Real Components
To build this on a breadboard, you need discrete MOSFETs with low threshold voltages so they fully switch at standard 5V logic levels. Do not use power MOSFETs like the IRF520; their gate capacitance is too high and their threshold voltages are too unpredictable for logic.
The Component Pick:
- NMOS: 2N7000 (N-channel, VGS(th) ≈ 2.0V, ID = 200mA). TO-92 package.
- PMOS: BS250 (P-channel, VGS(th) ≈ -1.5V, ID = 220mA). TO-92 package.
- Input Resistors: 10kΩ (x2) for pull-downs to prevent floating inputs.
- Output Resistor: 10kΩ pull-down to provide a defined LOW state when driving a high-impedance oscilloscope probe.
Step-by-Step Breadboard Verification
Follow this exact sequence to wire and test the gate. Never apply power while inserting components.
- De-energize and Prep: Ensure your bench power supply is OFF. Set it to 5.0V with a current limit of 100mA. Connect the red rail to VDD and the blue rail to GND.
- Place the Transistors: Insert the two BS250 (PMOS) and two 2N7000 (NMOS) transistors across the breadboard center trench. Ensure the flat faces are facing you. For the 2N7000, pins are Source(1), Gate(2), Drain(3). For the BS250, pins are Source(1), Gate(2), Drain(3). Verify datasheets for your specific manufacturer, as pinouts can vary.
- Wire the Pull-Up Network: Connect the Sources of both BS250s to the VDD rail. Connect their Drains together to form the OUT node.
- Wire the Pull-Down Network: Connect the Drain of the first 2N7000 (Q3) to the OUT node. Connect its Source to the Drain of the second 2N7000 (Q4). Connect the Source of Q4 to GND.
- Wire the Gates (Inputs): Connect the Gate of Q1 and Q3 together (IN_A). Connect the Gate of Q2 and Q4 together (IN_B).
- Install Pull-Downs: Insert a 10kΩ resistor from IN_A to GND, and another 10kΩ from IN_B to GND. This guarantees a default LOW state when no signal is applied.
- Test Sequence: Turn on the power supply. Use a digital multimeter (DMM) set to DC Voltage. Probe the OUT node.
- With both inputs tied to GND via the 10k resistors, OUT should read ~5.0V (HIGH).
- Use a jumper wire to manually pull IN_A to VDD. OUT should remain ~5.0V.
- Pull both IN_A and IN_B to VDD simultaneously. OUT should drop to < 0.1V (LOW).
Decision Tree: Picking Your Gate Implementation
When designing a system that requires NAND logic, do not default to discrete transistors unless you are prototyping for educational purposes or operating in extreme radiation environments where discrete layout is required. Use this decision matrix to select the correct physical implementation.
| Design Constraint | Recommended Topology / Part | Why This Wins |
|---|---|---|
| Standard 5V logic, high speed (>20MHz), automated PCB assembly | 74HC00 (HC-family CMOS) | Optimized for 5V, symmetrical drive strength, low propagation delay (~15ns). |
| Wide supply voltage (3V to 15V), battery-operated, low speed | CD4011B (4000-series CMOS) | Tolerates wide VDD ranges, extremely low static draw, but slower switching. |
| Interfacing 5V logic to 12V/24V industrial relays | CD40109B Level Shifter + CD4011 | Protects low-voltage logic from high-voltage inductive kickback. |
| Learning transistor physics, bench education, custom analog-logic hybrids | CD4007UB Discrete Array | Provides raw access to individual MOSFET gates/drains for probing and custom feedback loops. |
The Default Recommendation: If you are wiring a digital logic project on a breadboard or designing a standard PCB, buy a 74HC00 quad NAND IC. It costs roughly $0.50, contains four perfectly matched NAND gates, eliminates the wiring complexity of discrete MOSFETs, and includes internal protection diodes that prevent the shoot-through destruction common in raw discrete builds. Reserve the discrete CD4007UB or 2N7000/BS250 builds strictly for bench-side learning to visualize the underlying physics of the circuit diagram of gates.
