The standard discrete circuit diagram of a NOT gate (inverter) relies on an NPN bipolar junction transistor (BJT) wired in a common-emitter configuration. To build a functional 5V logic inverter on your bench, you need exactly three components: one NPN transistor (like the 2N3904), one collector pull-up resistor ($R_C$), and one base-limiting resistor ($R_B$). When the input at the base is HIGH, the transistor saturates and pulls the output LOW; when the input is LOW, the transistor cuts off and the pull-up resistor drives the output HIGH.
While modern designs typically use integrated circuits like the 74HC04, understanding the discrete topology is critical for interfacing custom sensors, driving higher-voltage loads from low-voltage logic, and debugging board-level failures. Below is the complete design walkthrough, node mapping, and failure-mode analysis for a 5V discrete NOT gate.
Discrete NOT Gate Topology and Node Mapping
The circuit relies on four primary nodes to manage logic states and power distribution:
- Node A ($V_{CC}$): The positive supply rail (typically 5V or 3.3V). Connects to the top of the pull-up resistor.
- Node B ($V_{IN}$): The logic input. Connects through the base resistor to the transistor's base.
- Node C ($V_{OUT}$): The logic output. Tapped at the junction of the pull-up resistor and the transistor's collector.
- Node D ($GND$): The ground reference. Connects to the transistor's emitter.
Why Common-Emitter Over the Alternative?
You might wonder why we don't use a common-collector (emitter-follower) topology, which is simpler to wire. An emitter follower outputs $V_{IN} - V_{BE}$ (approximately $V_{IN} - 0.7V$). If you feed it 5V, the output is 4.3V. If you feed it 0V, the output is 0V. It follows the input; it does not invert it. Furthermore, an emitter follower cannot pull the output all the way to the positive rail, resulting in degraded logic HIGH levels. The common-emitter topology is mandatory for inversion because taking the output from the collector allows the circuit to swing between $V_{CE(sat)}$ (near 0V) and $V_{CC}$ (full rail voltage).
Component Selection and Design Walkthrough
Let's design a 5V NOT gate capable of driving a standard logic input or a small indicator LED. We will use the ubiquitous ON Semiconductor 2N3904 NPN transistor.
1. Sizing the Pull-Up Resistor ($R_C$)
The pull-up resistor limits the current when the transistor is fully ON (saturated). We want a collector current of 5mA. Assuming a saturation voltage $V_{CE(sat)}$ of 0.2V:
$R_C = (V_{CC} - V_{CE(sat)}) / I_C = (5V - 0.2V) / 0.005A = 960\Omega$
Selected Value: The nearest standard E12 value is 1kΩ. This yields an actual $I_C$ of 4.8mA, which is perfectly safe and sufficient.
2. Sizing the Base Resistor ($R_B$)
To ensure the transistor acts as a hard switch (fully saturated) rather than a linear amplifier, we must overdrive the base. A standard rule of thumb is to force a $eta$ of 10 to 20 (known as forced beta). Let's aim for a forced $eta$ of 10.
$I_{B(required)} = I_C / 10 = 4.8mA / 10 = 0.48mA$
Accounting for the base-emitter voltage drop ($V_{BE} \approx 0.7V$) when the input is HIGH (5V):
$R_B = (V_{IN} - V_{BE}) / I_{B(required)} = (5V - 0.7V) / 0.00048A = 8,958\Omega$
Selected Value: We will use a standard 10kΩ resistor. This provides $I_B = 0.43mA$, resulting in a forced $eta$ of ~11, guaranteeing deep saturation without wasting excessive current.
Behavior Matrix and Failure Mode Contrast
Understanding how the circuit behaves under normal and fault conditions is what separates a hobbyist from a competent designer. Below is the logic behavior followed by the failure-mode contrast.
| Input State (Node B) | Transistor State | Output Voltage (Node C) | Logic Output |
|---|---|---|---|
| LOW (0V) | Cut-off (Open switch) | 5.0V (Pulled up via $R_C$) | HIGH (1) |
| HIGH (5V) | Saturated (Closed switch) | ~0.2V ($V_{CE(sat)}$) | LOW (0) |
What Breaks at the Extremes?
Discrete logic is highly vulnerable to component faults. Here is the failure-mode contrast when elements short or open:
- $R_B$ Shorts (Base tied directly to $V_{IN}$): If the input goes HIGH, base current is limited only by the driving source's internal impedance. This will likely exceed the 2N3904's maximum base current rating, destroying the base-emitter junction, and potentially frying the microcontroller GPIO pin driving it.
- $R_C$ Opens (Pull-up resistor fails or is omitted): When the input is LOW, the transistor turns off, but Node C has no path to $V_{CC}$. The output 'floats' (high impedance). It will read erratic voltages on a multimeter and fail to drive any subsequent logic gate HIGH.
- Collector-to-Emitter Short: The output is permanently stuck at ~0V (Logic LOW). The 1kΩ pull-up resistor will continuously dissipate $V^2/R = 25mW$, which is well within its 1/4W rating, so the resistor won't burn, but the logic function is dead.
Step-by-Step Breadboard Testing Procedure
Follow these exact steps to build and verify the circuit. You will need a breadboard, a 5V power supply, a 2N3904, a 1kΩ resistor, a 10kΩ resistor, and a digital multimeter (DMM).
- Identify the Pinout: Hold the 2N3904 with the flat side facing you and the legs pointing down. From left to right, the pins are Emitter (E), Base (B), and Collector (C).
- Establish Power Rails: Connect your 5V supply to the red breadboard rail (Node A) and GND to the black rail (Node D).
- Place the Transistor: Insert the 2N3904 across the center trench. Connect the Emitter (left pin) directly to the GND rail.
- Wire the Pull-Up ($R_C$): Insert the 1kΩ resistor. Connect one leg to the 5V rail and the other leg to the Collector (right pin) of the transistor. This junction is your Node C ($V_{OUT}$).
- Wire the Base Limiter ($R_B$): Insert the 10kΩ resistor. Connect one leg to the Base (middle pin) and leave the other leg exposed in an empty row to serve as your Node B ($V_{IN}$).
- Verify the LOW Input State: Jumper Node B to GND. Set your DMM to DC Voltage. Place the black probe on GND and the red probe on Node C. The meter should read 5.0V (±0.1V).
- Verify the HIGH Input State: Move the Node B jumper to the 5V rail. Measure Node C again. The meter should read between 0.1V and 0.3V (confirming $V_{CE(sat)}$).
Frequently Asked Questions
How to draw a circuit diagram of a NOT gate using MOSFETs?
To draw a MOSFET-based NOT gate, replace the NPN BJT with an N-channel MOSFET (like the 2N7000). The topology remains identical: the drain connects to the pull-up resistor, the source connects to GND, and the gate connects to the input. However, because a MOSFET gate draws virtually zero steady-state current, you can omit the base-limiting resistor ($R_B$). It is best practice to add a 10kΩ pull-down resistor from the gate to GND to prevent the output from floating if the input signal is disconnected, and a small series gate resistor (e.g., 100Ω) to dampen high-frequency ringing.
Why does my discrete NOT gate circuit diagram output float when the input is low?
If your output floats (reads random millivolts or picks up 60Hz mains noise) when the input is LOW, your pull-up resistor ($R_C$) is either missing, open-circuited, or connected to the wrong node. In a common-emitter configuration, the transistor can only pull the output to ground; it cannot source current. The pull-up resistor is strictly responsible for providing the HIGH state. Verify continuity between Node A ($V_{CC}$) and Node C ($V_{OUT}$) with the power off.
Can I cascade multiple discrete NOT gate circuits without signal degradation?
Yes, but you must account for loading effects. Unlike buffered CMOS ICs (like the Texas Instruments 74HC04), a discrete BJT inverter has a relatively low input impedance when HIGH (determined by $R_B$ and the transistor's $eta$). If you cascade them directly, the second gate's base current will pull down the first gate's output voltage. To cascade them reliably, increase the pull-up resistor ($R_C$) to 4.7kΩ or 10kΩ to stiffen the voltage source, or insert an emitter-follower buffer stage between the inverters to provide current gain.
