When reviewing a power supply schematic, a diagram of short circuit conditions isn't usually drawn as a primary feature; rather, it represents a catastrophic fault state where the output node bypasses the load resistance directly to ground. If your topology lacks active protection, this single fault will vaporize trace copper, destroy pass transistors, or trigger upstream breakers. Designing for the short-circuit extreme is just as critical as designing for nominal operation.

In this guide, we will dissect a discrete constant-current limiting topology, analyze its behavior across normal, open, and shorted extremes, and walk through a breadboard-safe design using real component values. By the end, you will know exactly how to size your sense resistors, manage thermal dissipation, and safely induce a short on your bench to verify your protection circuitry.

Decoding the Topology: Nodes and Current Limiting

To protect a load, we use a two-transistor constant-current limiter. This topology monitors the voltage drop across a sense resistor and actively chokes the base drive to the main pass transistor when the current exceeds a set threshold. Unlike a simple fuse, this circuit clamps the current and automatically resets when the fault is removed.

Here is the node mapping for our 12V-to-5V protected supply topology:

  • Node A ($V_{in}$): Unregulated 12V DC input.
  • Node B ($V_{base}$): Base of the main NPN pass transistor (Q1). Biased via a 1kΩ pull-up resistor to Node A, and regulated by a 5.6V Zener diode to ground.
  • Node C ($V_{emitter}$): Emitter of Q1. This is the top of our current sense resistor.
  • Node D ($V_{out}$): The bottom of the sense resistor and the positive terminal for the load. This is the node that gets shorted to ground during a fault.
  • Node E (GND): Common ground reference.

The protection mechanism relies on a secondary NPN transistor (Q2). The base of Q2 is tied to Node C, and its emitter is tied to Node D. When the voltage difference between Node C and Node D (the voltage across the sense resistor) reaches approximately 0.6V, Q2 turns on. Q2 then steals base current from Q1 (Node B), forcing Q1 out of saturation and into its active/limiting region, effectively clamping the maximum current.

Topology Behavior: Normal, Open, and Shorted Extremes

Understanding how voltages and currents shift during a fault is the key to reading a diagram of short circuit faults on a bench. The table below maps the exact electrical behavior of our topology across four distinct load states. Notice how $V_{sense}$ acts as the hard ceiling for the circuit's current delivery.

Load State $R_{load}$ $V_{out}$ (Node D) $I_{load}$ $V_{sense}$ (C to D) Q1 Pass State
Nominal 10 Ω 5.0V 0.50A 0.34V Active (Linear)
Heavy Load 2 Ω 2.0V 1.00A (Clamped) 0.68V Limiting (Active)
Open Circuit ∞ Ω 5.0V 0.00A 0.00V Cutoff / Micro-amp
Dead Short 0 Ω 0.0V 1.00A (Clamped) 0.68V Deep Limiting (High $V_{CE}$)
Bench Insight: In the "Dead Short" row, $V_{out}$ collapses to 0V, but the current remains locked at 1.00A. The entire 12V input potential is now dropped across Q1 (from Node A to Node C). This is where thermal destruction happens if the pass transistor is not properly heatsinked.

Design Walkthrough: Sizing a 1A Protected Supply

Let's pick real component values to build this on a breadboard. Our target is a 5V output capable of delivering up to 1A, with hard current limiting at exactly 1A.

1. Sizing the Sense Resistor ($R_{sense}$)

The limit triggers when the base-emitter junction of Q2 (a standard 2N3904 NPN) reaches ~0.6V. Using Ohm's Law:

$$R_{sense} = \frac{V_{be(Q2)}}{I_{limit}} = \frac{0.6V}{1.0A} = 0.6\Omega$$

Since 0.6Ω is not a standard E12 value, we select the next closest standard value: 0.68Ω. This shifts our actual trip point slightly:

$$I_{actual} = \frac{0.6V}{0.68\Omega} \approx 0.88A$$

Power Rating: At 0.88A, the resistor dissipates $P = I^2R = (0.88)^2 \times 0.68 = 0.52W$. We must use a 2W thick-film or wirewound resistor to ensure it survives continuous short-circuit conditions without drifting in value due to heat.

2. Selecting the Pass Transistor (Q1)

Q1 must handle the input voltage and the limited current. We choose the TIP31C (NPN, TO-220 package, $V_{CEO}$ = 100V, $I_C$ = 3A).

3. The Base Drive Network

We need a 5V output. A 5.6V Zener diode (BZX55C5V6) from Node B to Ground provides the reference. Accounting for the ~0.6V $V_{be}$ drop of Q1, the emitter (Node C) sits at roughly 5.0V. A 1kΩ pull-up resistor from the 12V rail (Node A) to Node B supplies the base current. Under a short circuit, Q2 steals this current, so the 1kΩ resistor must be sized to provide enough base drive for Q1 during nominal operation, but not so much that it overheats Q2 during a fault. 1kΩ provides ~6.4mA of base drive, which is safe for the 2N3904 (Q2) to shunt to ground.

Why This Topology Over a Polyfuse (PTC)?

You might wonder why we build a discrete transistor limiter instead of just dropping a 1A resettable PTC fuse in series with the output. PTCs have a high internal resistance (often 0.1Ω to 0.5Ω), which causes significant voltage droop under normal loads. Furthermore, PTCs are thermally triggered; they take hundreds of milliseconds to trip, allowing high current spikes to pass through and potentially damage sensitive downstream microcontrollers. The BJT topology reacts in microseconds, clamping the current instantly with minimal nominal voltage drop.

Breadboard Testing: Safely Inducing the Short

Testing a short circuit on a breadboard requires discipline. Breadboard contacts are rated for roughly 1A to 2A max, and thin jumper wires will melt if a fault occurs before your protection kicks in. Follow these exact steps to verify your design safely.

  1. Prepare the Measurement Gear: Set your bench power supply to 12.0V with a hard current limit of 1.5A. This acts as your ultimate failsafe. Set two multimeters: one to measure DC voltage (probes on Node D and GND), and one to measure DC current (in series with the load path).
  2. Wire the Nominal Load: Connect a 10Ω, 5W power resistor between Node D and GND. Power on the supply. You should read ~5.0V at Node D and ~0.5A on the current meter. The sense resistor should remain cool to the touch.
  3. Verify the Trip Point: Swap the 10Ω resistor for a 2Ω resistor. The voltage at Node D will drop to roughly 1.76V, and the current will clamp at ~0.88A. The sense resistor will begin to get warm.
  4. Induce the Controlled Short: Remove the load resistor entirely. Take a short, thick piece of 18 AWG solid copper wire and bridge Node D directly to the GND rail.
  5. Observe the Clamp: The voltage meter will read 0.0V (or a few millivolts representing wire resistance). The current meter will read exactly 0.88A. The circuit has successfully entered the dead-short state.
  6. Thermal Verification: Keep the short applied for exactly 10 seconds. Carefully hover your finger over the TIP31C transistor. It will be extremely hot. Remove the short; the voltage at Node D should instantly snap back to 5.0V.

Failure Modes: What Breaks at the Extremes

Designing the circuit is only half the battle; understanding how it fails is what separates hobbyists from engineers. When you look at a diagram of short circuit thermal limits, you are looking at the Safe Operating Area (SOA) of the pass transistor.

The Thermal Runaway Extreme

In our dead-short test, $V_{out}$ is 0V, meaning the entire 12V from Node A is dropped across the Collector-Emitter junction of Q1. With the current clamped at 0.88A, the power dissipation in Q1 is:

$$P_{Q1} = V_{CE} \times I_C = 12V \times 0.88A = 10.56W$$

Critical SOA Warning: A bare TIP31C in a TO-220 package has a junction-to-ambient thermal resistance ($R_{\theta JA}$) of roughly 62°C/W. Dissipating 10.56W will raise the junction temperature by over 650°C above ambient in seconds, instantly destroying the silicon. You must attach a heatsink rated for at least 10W (approx 5°C/W) if this circuit is expected to sustain a short circuit for more than a few seconds. Alternatively, implement foldback current limiting, which reduces the current clamp as the output voltage drops, drastically cutting thermal dissipation during a dead short.

The Open-Circuit Extreme

What happens if the load is completely disconnected? Node D is floating, but held at 5V by the Zener reference. Q1 is in cutoff, conducting only microamps of leakage current. The danger here isn't thermal; it's transient. If a heavy capacitive load is suddenly connected to Node D, the inrush current will momentarily look like a dead short. Q2 will slam on, choking Q1. If the base-drive resistor (1kΩ) is too large, Q1 might not recover quickly enough, causing the output voltage to latch in a low state until the power is cycled. Always test your protection topology with the maximum expected capacitive load (e.g., 1000µF) attached to ensure it powers up cleanly without tripping its own limiter.

By mapping the nodes, sizing the sense resistor for exact trip points, and respecting the SOA limits of your pass elements, you transform a catastrophic short-circuit fault into a manageable, recoverable event. Your schematic's diagram of a short circuit is no longer a blueprint for failure, but a verified test condition.