De Morgan's Law states that inverting the output of an AND gate produces the exact same logic as an OR gate with inverted inputs, and vice versa. In physical circuits, this theorem changes how we route signals, allowing us to swap gate types, minimize IC count, and convert between active-high and active-low logic without altering the system's physical behavior. Whether you are writing PLC ladder logic, routing FPGA pins, or substituting parts on the workbench, this rule is the bridge between positive and negative logic.
The Core Equivalencies and Truth Tables
At the silicon level, logic gates are built from CMOS transistors. Because of how PMOS and NMOS networks are arranged, an AND gate is actually a NAND gate followed by an inverter. De Morgan's theorems formalize this hardware reality into Boolean algebra. According to All About Circuits, these two rules form the foundation of logic minimization.
| Rule | Boolean Expression | Gate Equivalent | Physical Meaning |
|---|---|---|---|
| Rule 1 (NAND to OR) | NOT (A AND B) = (NOT A) OR (NOT B) | NAND gate = OR gate with bubbled inputs | An active-low input OR function is identical to a standard NAND function. |
| Rule 2 (NOR to AND) | NOT (A OR B) = (NOT A) AND (NOT B) | NOR gate = AND gate with bubbled inputs | An active-low input AND function is identical to a standard NOR function. |
Notice the critical mechanical shift: when you break the inversion bar (the NOT operator) over a grouped expression, the operator underneath must flip from AND to OR, or OR to AND. If you forget to flip the operator, your circuit will fail.
Worked Example: 24V Industrial E-Stop Interlock
Let's look at how this changes a real installation. Imagine you are wiring a 24V DC safety interlock for a CNC router using three Normally Closed (NC) emergency stop pushbuttons.
- Normal State: Buttons are unpressed. Contacts are closed. Voltage at the PLC input is 24V (Logic 1).
- Fault State: Any button is pressed. Contacts open. Voltage at the PLC input drops to 0V (Logic 0).
You need the machine to halt (Logic 1 output to the main contactor relay) if any of the three buttons are pressed. Mathematically, you want an OR function: Halt = (NOT A) OR (NOT B) OR (NOT C).
If you try to use a standard 3-input OR gate (like a 74HC4075), it will fail. An OR gate expects active-high inputs to trigger a high output. Feeding it 0V (Logic 0) when a button is pressed will not trigger the halt. You would need to add three separate inverter ICs to flip the signals before the OR gate, wasting board space and propagation time.
Applying De Morgan's Law:
Halt = (NOT A) OR (NOT B) OR (NOT C)
Halt = NOT (A AND B AND C)
The expression NOT (A AND B AND C) is the exact definition of a 3-input NAND gate. By applying De Morgan's Law, we realize we can wire the raw 24V NC signals directly into a 3-input NAND gate (such as the 74HC10 or a discrete NAND IC rated for 24V). When all buttons are normal (1, 1, 1), the NAND output is 0. When any button is pressed (e.g., 0, 1, 1), the NAND output immediately goes HIGH (1), triggering the contactor. You saved three inverters and simplified the wiring harness.
Where You Meet This in Practice
You will rarely sit down and write out Boolean proofs for a simple home wiring job, but De Morgan's Law operates constantly in the background of modern electrical and electronic systems.
attachInterrupt(digitalPinToInterrupt(pin), ISR, FALLING)). When routing external hardware to these pins, you use De Morgan's theorems to design the pull-up resistor networks and switch matrices so that a 'break' in a security loop correctly registers as a logic LOW trigger.
- PLC Ladder Logic: When converting a schematic with series/parallel relay contacts into PLC code, NC contacts are represented as 'NOT' instructions. De Morgan's law allows programmers to simplify complex nested branches, converting parallel NOT branches into a single series AND block, reducing scan time.
- FPGA/CPLD Synthesis: Hardware description languages (Verilog/VHDL) compile down to Look-Up Tables (LUTs). Synthesis engines use De Morgan's laws to map your code into the physical NAND/NOR structures native to the silicon fabric, optimizing for the lowest gate count.
- Bench Troubleshooting: When tracing a fault on a legacy control board with a dead 74HC32 (OR gate), you can temporarily jury-rig a replacement using a 74HC00 (NAND gate) and a 74HC04 (Hex Inverter) by applying the equivalencies, getting the machine running while you wait for the exact OEM part to ship.
Decision Tree: Bench Substitutions and Part Selection
When you are at the bench and realize you are out of the specific logic IC you need, use this decision path to substitute using universal gates. NAND and NOR gates are 'universal' because, via De Morgan's Law and basic inversion, they can build any other logic function.
| Your Goal | What You Have in the Bin | Action Required (De Morgan / Inversion) | Concrete Part to Use |
|---|---|---|---|
| Need a 2-input OR gate | Only have 2-input NAND gates | Invert both inputs, then feed into NAND. (Requires 3 NAND gates total). | 74HC00 (Quad 2-Input NAND) |
| Need a 2-input AND gate | Only have 2-input NOR gates | Invert both inputs, then feed into NOR. (Requires 3 NOR gates total). | 74HC02 (Quad 2-Input NOR) |
| Need a NOT gate (Inverter) | Only have 2-input NAND gates | Tie both inputs of the NAND gate together. (A NAND A = NOT A). | 74HC00 (Use 1 gate of the Quad IC) |
| Need an Active-Low OR (Wired-AND) | Diodes and Pull-up Resistors | Skip logic ICs entirely; use diode-resistor logic (hardware De Morgan). | 1N4148 Diodes + 10kΩ Pull-up |
Default Recommendation: If you are stocking a lab or designing a custom control board from scratch, standardize on the 74HC00 (NAND) and 74HC04 (Inverter). Between those two ICs, you can construct any logic function required by the system, reducing your BOM (Bill of Materials) and inventory overhead.
Common Confusions: Bubble Pushing vs. Distribution
Even experienced technicians and engineering students trip over two specific edge cases when applying these rules.
1. Forgetting to Change the Operator
The most common error is breaking the inversion bar but leaving the operator the same.
Wrong: NOT (A AND B) = (NOT A) AND (NOT B)
Right: NOT (A AND B) = (NOT A) OR (NOT B)
If you do this in a PLC program, your machine will crash because the safety interlocks will require all faults to be present simultaneously to trigger a halt, rather than any fault.
2. Confusing De Morgan's with the Distributive Law
De Morgan's deals exclusively with inversions over grouped terms. The Distributive Law deals with expanding terms without inversions.
Distributive: A AND (B OR C) = (A AND B) OR (A AND C).
As noted in Electronics Tutorials, mixing these up leads to fundamental errors in Karnaugh mapping and logic minimization. Always check if there is a 'NOT' bubble over the entire group before deciding which rule to apply.
3. 'Bubble Pushing' Errors on Schematics
In schematic design, engineers use 'bubble pushing' to visualize De Morgan's Law. If you see a NAND gate, you can draw it as an OR gate with bubbles on the inputs. The confusion arises when the signal feeding that gate is already active-low. Two bubbles (one from the source, one from the gate input) cancel each other out. Always trace the net label back to the source to verify the true active state of the voltage.
Frequently Asked Questions
Does De Morgan's Law apply to more than two inputs?
Yes. The rule scales infinitely. NOT (A AND B AND C AND D) is exactly equal to (NOT A) OR (NOT B) OR (NOT C) OR (NOT D). This is heavily utilized in 4-input and 8-input logic ICs like the 74HC20 or 74HC30.
Can I use De Morgan's Law for analog circuits?
No. De Morgan's theorems are strictly for Boolean (digital) algebra, where states are binary (1/0, High/Low, True/False). Analog circuits dealing with continuous voltage, RMS values, or impedance rely on Kirchhoff's and Ohm's laws, not Boolean transformations.
Why do NAND gates dominate digital silicon design?
Because of De Morgan's Law and the physical layout of CMOS transistors. A NAND gate requires fewer transistors and has faster switching speeds (due to electron mobility in NMOS pull-down networks) compared to an AND gate. Since De Morgan's proves you can build any OR/AND function out of NANDs, silicon foundries standardize on NAND-based standard cell libraries to maximize die density and speed.
