For a 12V to 3.3V buck converter operating in Continuous Conduction Mode (CCM), the theoretical duty cycle derived from the steady-state voltage waveforms is exactly 27.5%. Using the ideal formula D = Vout / Vin, we substitute 3.3V / 12V = 0.275. At a standard 500 kHz switching frequency (where the period Ts = 2 μs), this converts directly to a high-side MOSFET on-time (ton) of 550 ns and an off-time (toff) of 1450 ns. If you are probing the switch node (SW) on your bench with an oscilloscope, these are the exact time-domain measurements you should see before accounting for parasitic ringing and dead-time.
However, this 27.5% figure assumes an ideal synchronous buck topology. If you are using a non-synchronous design with a Schottky freewheeling diode (e.g., Vf = 0.4V), the formula shifts to D = (Vout + Vf) / (Vin + Vf). Substituting those values yields 3.7V / 12.4V, pushing the required duty cycle up to 29.8% (ton = 596 ns). The assumption of CCM and the specific component voltage drops are what fix this answer; change the mode or the diode, and the waveform timing shifts entirely.
The Core Waveform Conversions and IC Limits
Translating oscilloscope waveform measurements back into design parameters requires knowing the hard limits of your controller IC. Every buck converter has a minimum on-time (ton(min)) and a maximum duty cycle. If your calculated ton falls below the IC's minimum on-time, the converter will skip pulses or drop out of regulation, completely invalidating the standard CCM waveform conversions.
| IC Part Number | Switching Freq (fsw) | Min On-Time (ton(min)) | Max Duty Cycle | Typical Use Case |
|---|---|---|---|---|
| TI TPS5430 | 500 kHz | 120 ns | 85% | 12V/24V to 5V/3.3V general purpose |
| MPS MP2315S | 1.4 MHz | 40 ns | 95% | High-density 5V to 1.2V core rails |
| ADI LT8640S | 2 MHz | 30 ns | 99% (Dropout) | Automotive 24V to 3.3V/5V logic |
| TI LM5160 | 1 MHz (Adj) | 110 ns | 99% (Dropout) | 48V industrial bus to 12V/5V |
Using the TI Power Stage Designer Tool or Analog Devices LTpowerCAD, you can cross-reference these IC limits against your calculated waveform timings. For instance, if you attempt to step down 24V to 1.2V at 1.4 MHz using the MP2315S, your theoretical ton is roughly 71 ns. This is safely above the 40 ns minimum on-time, meaning the waveforms will remain stable and continuous.
Neighboring Output Values (±20% Tolerance Band)
Component tolerances, feedback resistor drift, and load regulation mean your output voltage is rarely exactly 3.300V. Here is how the waveform timing converts across a ±20% band of a 3.3V nominal target (assuming 12V input, 500 kHz, ideal CCM):
| Vout Measured | Variance | Duty Cycle (D) | ton (ns) | toff (ns) |
|---|---|---|---|---|
| 2.64V | -20% | 22.0% | 440 ns | 1560 ns |
| 3.30V | Nominal | 27.5% | 550 ns | 1450 ns |
| 3.96V | +20% | 33.0% | 660 ns | 1340 ns |
Voltage Scaling: 12V vs 48V vs Offline AC Mains
A common point of confusion is how buck converter waveform conversions shift when dealing with 120V AC, 230V AC, or 3-phase mains. A buck converter is strictly a DC-DC topology. It cannot process AC waveforms directly. If you are designing an offline power supply, the buck converter's input is the rectified and filtered DC bus after the bridge rectifier and Power Factor Correction (PFC) stage.
Here is how the input voltage shifts the buck converter's duty cycle for a fixed 12V output:
- 12V DC Input (Battery/Adapter): D = 12/12 = 100%. The converter operates in dropout or bypass mode. The SW waveform is a solid DC high; switching ceases.
- 48V DC Input (Telecom/Industrial): D = 12/48 = 25%. At 500 kHz, ton = 500 ns. You must ensure your IC's minimum on-time is well below 500 ns to avoid pulse-skipping.
- 120V AC Mains (Offline): After full-bridge rectification and bulk capacitance (no active PFC), the DC bus sits at roughly 160V-170V DC. D = 12/170 = 7.0%. ton drops to 140 ns. This requires a high-voltage buck IC with a very fast minimum on-time, or a flyback topology instead.
- 230V AC Mains (Offline): The rectified DC bus peaks near 325V DC. D = 12/325 = 3.6%. ton = 72 ns. Standard low-voltage buck ICs will fail here; you need specialized offline step-down controllers (like the MPS MP170) or a two-stage PFC + isolated DC-DC approach.
- 3-Phase AC (Industrial): The rectified DC bus exceeds 600V DC. A single-stage buck converter is entirely impractical and unsafe at this voltage differential. Isolated topologies (LLC resonant, phase-shifted full-bridge) are mandatory.
When Waveform Conversions Become Meaningless
The D = Vout / Vin conversion is a steady-state CCM equation. If you attempt to apply this math to the following scenarios, your calculated numbers will completely disagree with your oscilloscope measurements:
At light loads, the inductor current falls to zero before the switching period ends. The SW node waveform will show a distinct "dead time" where the voltage rings at the LC resonant frequency. In DCM, duty cycle is no longer a simple ratio of voltages; it becomes a function of load current, inductance, and switching frequency.
Modern ICs (like the TI TPS5430 in light-load conditions) skip switching cycles to improve efficiency. If you measure the SW node and see a 2 μs on-time followed by 15 μs of silence, the converter is pulse-skipping. Calculating a "duty cycle" from a single isolated pulse is meaningless for thermal or ripple analysis.
During startup, the internal error amplifier clamps the control voltage, artificially limiting ton to ramp the output voltage slowly. Similarly, during a massive load step (e.g., 0A to 3A in 1 μs), the converter will hit its maximum current limit or maximum duty cycle clamp. The waveforms during these transient events reflect the control loop's compensation network, not the steady-state voltage conversion ratio.
FAQ: Probing Buck Converter Waveforms
Q: Why does my measured ton look 20ns longer than my calculation?
A: You are likely measuring the SW node ringing. The true ton is measured from the moment the high-side MOSFET gate drive crosses the threshold (usually ~2.5V) to when it falls. Furthermore, non-synchronous controllers have a mandatory "dead time" (typically 20-50ns) where both MOSFETs are off to prevent shoot-through. This dead time eats into your theoretical toff and slightly alters the effective duty cycle.
Q: Can I use a standard 10:1 oscilloscope probe with the alligator ground clip to measure the SW node?
A: You can, but the 3-inch ground lead acts as an antenna, picking up the massive di/dt loop and showing massive voltage overshoot that isn't actually there. Always remove the plastic probe tip and ground clip, and use a ground spring (the short coil of wire included with your probe) to connect the probe ground directly to the ceramic output capacitor ground pad. This reduces the loop area and gives you a true representation of the SW node waveform.
