When you need to freeze a transient digital signal or expand the I/O lines on a microcontroller, the D latch (Data latch) is your fundamental building block. Unlike an edge-triggered flip-flop that only samples data on a clock edge, a D latch is transparent. It passes the Data (D) input directly to the Q output as long as the Enable (EN) pin is HIGH, and locks that state the moment EN drops LOW. If you are searching for a reliable d latch circuit diagram and truth table, you need more than just abstract logic gates—you need the exact timing specifications, propagation delays, and load derating curves that dictate whether your circuit will work on the bench or fail in the field.
The direct answer for standard logic families: a D latch outputs the logic state present at the D pin while EN is HIGH. When EN transitions LOW, the Q output holds its last state regardless of subsequent changes at D. Below is the complete reference data for designing, debugging, and implementing D latches using industry-standard ICs like the Texas Instruments SN74HC75 (CMOS) and SN74LS75 (Bipolar).
The D Latch Truth Table and Logic States
The truth table defines the logical behavior of the latch independent of the underlying silicon. Standardized under IEEE Std 91/91a for graphic symbols and JEDEC logic definitions, the table below maps the inputs to the next output state. Bookmark this section for quick logic verification when probing a board with a multimeter or logic analyzer.
| Data (D) | Enable (EN) | Q (Next State) | Q-Not (Next State) | Operating Mode |
|---|---|---|---|---|
| 0 | 1 (HIGH) | 0 | 1 | Transparent (Passes LOW) |
| 1 | 1 (HIGH) | 1 | 0 | Transparent (Passes HIGH) |
| X | 0 (LOW) | $Q_0$ | $\overline{Q_0}$ | Latched (Hold Previous State) |
Real-World IC Timing and Electrical Specs
Logic tables assume zero time delay, but on the bench, propagation delay ($t_{pd}$) and setup/hold times dictate your maximum clock frequency and signal integrity. The following data-dense table compares the two most common quad D-type latch ICs: the CMOS SN74HC75 and the older bipolar SN74LS75. All values are sourced from manufacturer datasheets at an ambient temperature of 25°C.
| Parameter | Symbol | SN74HC75 (CMOS, 5V) | SN74LS75 (Bipolar, 5V) | Unit |
|---|---|---|---|---|
| Propagation Delay (D to Q) | $t_{pd}$ | 14 (Typ) / 28 (Max) | 20 (Typ) / 35 (Max) | ns |
| Propagation Delay (EN to Q) | $t_{pd}$ | 16 (Typ) / 32 (Max) | 25 (Typ) / 40 (Max) | ns |
| Setup Time (D before EN falls) | $t_{su}$ | 5 (Min) | 20 (Min) | ns |
| Hold Time (D after EN falls) | $t_{h}$ | 0 (Min) | 5 (Min) | ns |
| Output Drive Current (Sink) | $I_{OL}$ | 4 (Min) | 8 (Min) | mA |
| Quiescent Supply Current | $I_{CC}$ | 0.08 (Max) | 18 (Typ) | mA |
Which Column Applies to Your Installation?
When reading timing columns in a CMOS datasheet, the base values above assume a specific supply voltage ($V_{CC}$ = 5V) and a specific capacitive load ($C_L$ = 15pF for HC series). If you are running the SN74HC75 at 3.3V to interface directly with an ESP32 or Raspberry Pi Pico, you must look at the 3.3V column in the datasheet. At $V_{CC}$ = 3.3V, the internal MOSFETs switch slower, and the maximum $t_{pd}$ (D to Q) increases from 28ns to approximately 45ns. Always match the voltage column to your actual logic rail, not the IC's absolute maximum rating.
How Derating Rows Modify the Base Value
Datasheets provide base timing at a light 15pF capacitive load. In a real circuit, every inch of PCB trace, every breadboard contact, and every downstream logic gate input adds parasitic capacitance. For the 74HC family, the datasheet includes a capacitive load derating factor. You must add approximately 0.8ns to the propagation delay for every additional 50pF of load capacitance. If your D latch is driving a long ribbon cable or multiple gate inputs totaling 100pF, your actual $t_{pd}$ will be closer to 30ns, not the 14ns typical value. Thermal derating also applies: operating at the industrial maximum of 85°C will push the 'Max' timing limits roughly 10-15% higher than the 25°C room-temperature baseline.
Gate-Level Circuit Diagram and Metastability
A standard transparent D latch is constructed from four cross-coupled NAND or NOR gates. The electronics-tutorials.ws sequential logic guide provides an excellent visual breakdown of this gate-level d latch circuit diagram. In CMOS ICs like the 74HC75, transmission gates (parallel NMOS and PMOS transistors) are often used instead of discrete NAND gates to reduce transistor count and minimize propagation delay skew between the true and complementary outputs.
The truth table shows a clean transition from 'Transparent' to 'Latched'. It does not show what happens if the D input changes state exactly as the Enable pin crosses the logic threshold voltage ($V_{IH}/V_{IL}$). This violates the setup ($t_{su}$) and hold ($t_{h}$) times, forcing the internal cross-coupled gates into a state of equilibrium where the output voltage hovers at $V_{CC}/2$. This is called metastability. The output may oscillate, take microseconds to resolve to a valid HIGH or LOW, or cause massive shoot-through current in downstream CMOS gates, leading to localized heating and logic faults.
Designing Around the Metastability Window
To prevent metastability in your circuit diagram, you must ensure the Data signal is completely stable before the Enable signal falls. If you are capturing asynchronous external signals (like a bouncing mechanical switch or an incoming UART byte), a single D latch is insufficient. You must cascade two D latches in series, clocked by the same system clock. The first latch may enter a metastable state, but the probability of that unresolved state propagating through the second latch drops exponentially, effectively synchronizing the asynchronous signal to your local clock domain.
When selecting your IC, match the logic family to your system. Use the 74HC series for low-power, modern microcontroller interfaces (3.3V or 5V). Reserve the 74LS series only for legacy 5V TTL bus repairs, as its higher quiescent current (18mA vs 0.08mA) and slower setup times make it a poor choice for new battery-powered or high-speed designs.
