A current mirror is an active circuit that copies a reference input current and forces an identical (or scaled) output current through a load, regardless of load resistance changes. If you are designing an analog front-end, biasing a differential pair, or trying to drive parallel LED strings without thermal runaway, you cannot rely on passive resistors alone. A current mirror changes the circuit's behavior by replacing fixed-resistance biasing with a high-impedance active current source that ignores supply voltage ripple and dynamically adapts to load variations.
The Core Mechanism and Thermal Coupling
To understand how this works on the bench, we rely on a single water analogy: imagine a master water pipe with a flow-restrictor (the reference resistor) and a flow-meter that physically links to a valve on a secondary pipe. Whatever flow the master pipe achieves, the linked valve forces the secondary pipe to match, even if the secondary pipe's downstream plumbing changes.
In a basic Bipolar Junction Transistor (BJT) current mirror, the "master pipe" is a diode-connected transistor (Q1). Its base and collector are shorted together, forcing it to operate in the active region with a fixed $V_{BE}$. The "secondary pipe" is Q2, which shares the exact same base-emitter voltage as Q1. Because the collector current of a BJT is exponentially dependent on $V_{BE}$, identical base-emitter voltages yield identical collector currents—provided the transistors are perfectly matched and at the exact same temperature.
A Worked Numeric Example: 1mA BJT Mirror
Let’s design a basic NPN mirror to source exactly 1mA into a load using a 5.0V logic supply.
First, we calculate the reference resistor ($R_{REF}$) that sets the master current:
$R_{REF} = (V_{CC} - V_{BE}) / I_{REF}$
$R_{REF} = (5.0V - 0.65V) / 0.001A = 4350\Omega$
We select a standard 4.3k$\Omega$ 1% tolerance resistor. The actual reference current becomes:
$I_{REF} = (5.0V - 0.65V) / 4300\Omega = 1.011mA$
Because Q1 and Q2 are monolithic and thermally coupled, $V_{BE1} = V_{BE2}$. Therefore, $I_{OUT} \approx I_{REF} = 1.011mA$. The load receives a steady 1.011mA whether it is a 100$\Omega$ resistor or a 1k$\Omega$ resistor, as long as Q2 remains in the active region (i.e., $V_{CE2} > V_{CE(sat)}$).
- Wire Q1 as a diode: Connect the base and collector of the first half of the BCM847 together, then route them through your 4.3k$\Omega$ resistor to $V_{CC}$.
- Link the bases: Tie the base of Q2 directly to the base of Q1.
- Ground the emitters: Connect both emitters to your common ground plane.
- Attach the load: Connect your load between $V_{CC}$ and the collector of Q2.
- Verify with a DMM: Measure the voltage drop across a 10$\Omega$ sense resistor placed in series with the load to confirm $I_{OUT}$ matches $I_{REF}$.
Where You Meet Current Mirrors in Practice
You might think current mirrors are strictly an integrated-circuit (IC) design trick, but they appear in discrete bench designs and commercial hardware constantly. According to foundational analog texts like those on All About Circuits, mirrors are the backbone of modern analog signal processing.
- Op-Amp Active Loads: Inside chips like the LM358 or TL072, current mirrors replace passive collector resistors in the differential input stage. This provides massive dynamic impedance, yielding the high open-loop gain required for precision amplification.
- Parallel LED Arrays: If you wire three parallel LED strings with simple current-limiting resistors, the string with the lowest forward voltage ($V_f$) will hog the current, heat up, drop its $V_f$ further, and eventually fail (thermal runaway). A multi-output current mirror forces identical current through every string, regardless of $V_f$ manufacturing bins.
- Audio Amplifier Biasing: In Class-AB discrete audio amplifiers, a current mirror is often used to bias the differential input pair, ensuring the quiescent current remains stable even as the power supply rails sag during heavy bass transients.
Bench Scenario: When a Basic Mirror Fails
Theoretical textbook examples assume ideal transistors. Real-world silicon has flaws. Here is a scenario where a basic two-transistor mirror fails on the bench, and how to diagnose it.
The Setup: You are biasing a high-side RF load at 12V using a 5V logic-level reference current of 2.0mA. You wire a basic two-transistor BJT mirror using discrete 2N3904s. Q1 (diode-connected) has its collector tied to its base, so $V_{CE1} = 0.7V$. Q2 (the output transistor) has its collector tied to the 12V load, meaning $V_{CE2} \approx 10V$.
The Numbers: You calculated $R_{REF}$ to yield exactly 2.0mA. You expect $I_{OUT} = 2.0mA$.
The Outcome: Your multimeter reads 2.36mA. The circuit is over-biasing the RF load, causing distortion and excess heat.
What Went Wrong: You ignored the Early Effect (base-width modulation). In a real BJT, the effective width of the base region shrinks as the collector-base reverse bias increases. This causes the collector current to increase slightly with $V_{CE}$. The relationship is modeled using the Early Voltage ($V_A$), which is roughly 100V for a 2N3904. The actual collector current is $I_C = I_{ideal} \times (1 + V_{CE} / V_A)$.
For Q1, the multiplier is $(1 + 0.7 / 100) = 1.007$.
For Q2, the multiplier is $(1 + 10 / 100) = 1.10$.
The ratio of Q2 to Q1 is $1.10 / 1.007 = 1.092$.
Therefore, a 2.0mA reference yields $2.0mA \times 1.092 = 2.184mA$ (plus additional errors from discrete $V_{BE}$ mismatch, pushing it to 2.36mA).
Common Confusions: Mirrors vs. Resistors vs. CRDs
Beginners frequently confuse a current mirror with a simple current-limiting resistor or a Constant Current Diode (CRD). A CRD (which is essentially a JFET with its gate tied to its source) limits current to a fixed maximum, but it does not actively track a dynamic reference. A current mirror is a copier, not just a limiter. As detailed in Electronics Tutorials, the dynamic impedance of a mirror is vastly superior to passive alternatives.
| Feature | Current Limiting Resistor | Constant Current Diode (CRD) | Active Current Mirror |
|---|---|---|---|
| Primary Function | Drop voltage / limit max current | Clamp current to a fixed max | Copy and force a specific reference current |
| Dynamic Impedance | Low (equals resistance value) | Medium (few k$\Omega$) | Very High (tens to hundreds of k$\Omega$) |
| Supply Rejection (PSRR) | Poor (current varies with $V_{CC}$) | Good | Excellent |
| IC Die Area Cost | Massive (resistors waste silicon) | Not applicable (discrete only) | Microscopic (transistors are cheap on silicon) |
Frequently Asked Questions
Can I build a current mirror with MOSFETs instead of BJTs?
Yes, and MOSFET mirrors are standard in CMOS IC design because they draw zero gate current, eliminating the "base current steal" error inherent in BJTs. However, on the discrete bench, MOSFETs suffer from massive threshold voltage ($V_{th}$) mismatch. Two discrete 2N7000s might have $V_{th}$ values differing by 500mV, which will completely ruin the current matching. If you must use discrete MOSFETs, add source degeneration resistors (e.g., 10$\Omega$ to 100$\Omega$) to swamp out the $V_{th}$ mismatch.
What is "base current steal" and how does it affect my BJT mirror?
In a basic two-BJT mirror, the reference current ($I_{REF}$) must supply the collector current of Q1 plus the base currents for both Q1 and Q2. If your transistors have a low $\beta$ (current gain), the base currents "steal" a significant portion of $I_{REF}$, making $I_{OUT}$ noticeably lower than expected. For high-precision work, use a three-transistor Wilson mirror or add a beta-helper transistor to buffer the base node.
Why does my mirror oscillate when driving a capacitive load?
Current mirrors have very high output impedance. When you connect a highly capacitive load (like a long coaxial cable or a large bypass capacitor) to the output of a mirror, the capacitance interacts with the high output impedance to create a low-frequency pole, introducing phase shift and causing high-frequency oscillation. Always isolate capacitive loads from the mirror's collector using a small series resistor (e.g., 50$\Omega$) or a buffer stage.
