A current mirror MOSFET circuit forces two or more field-effect transistors to share identical drain currents by tying their gates together and forcing one transistor into a diode connection. Unlike BJT current mirrors, which suffer from base-current errors, MOSFET mirrors offer near-infinite input impedance at the gate, making them the backbone of precision analog biasing, active loads in differential amplifiers, and constant-current LED drivers.

However, the difference between a textbook schematic and a working bench circuit lies entirely in threshold voltage (Vgs(th)) matching and thermal coupling. If you build a mirror out of two random discrete 2N7000s, the output current will drift wildly. To get precision, you need monolithic matched pairs. Below is the definitive guide to selecting, biasing, and testing current mirror MOSFETs for real-world analog applications.

Safe Defaults: Selecting Matched MOSFET Pairs

The most common mistake hobbyists and junior engineers make is attempting to build a precision current mirror with discrete, off-the-shelf MOSFETs. Discrete parts have massive binning tolerances for Vgs(th)—often varying by ±500mV between two parts from the same reel. For a current mirror, the reference and output transistors must be fabricated on the same silicon die to ensure identical thermal characteristics and threshold voltages.

Table 1: Recommended Matched MOSFET Pairs for Current Mirrors
Part Number Type Vds Max Id Max Vgs(th) Match Package Typical Price
ALD1102A Dual NMOS 10.6V 30mA ±1mV (Tight) 8-pin DIP / SOIC $2.50
ALD1103 Dual PMOS 10.6V 30mA ±1mV (Tight) 8-pin DIP / SOIC $2.80
CD4007UBE Array (N/P) 20V 10mA ±50mV (Moderate) 14-pin DIP $0.65
2N7000 Discrete NMOS 60V 200mA ±500mV (Poor) TO-92 $0.10
Bench Tip: For 90% of low-power analog prototyping (sensor biasing, sub-10mA active loads), the ALD1102A (NMOS) and ALD1103 (PMOS) from Advanced Linear Devices are the undisputed safe defaults. They are specifically laser-trimmed for tight Vgs(th) matching.

Symbol, Pinout, and Operation Regions

In a basic NMOS current mirror schematic, you will see two transistors, M1 and M2. M1 is the 'reference' FET. Its Drain is shorted directly to its Gate, forcing it into a diode-connected state. M2 is the 'mirroring' FET. The Gates of M1 and M2 are tied together, and their Sources are tied to ground.

Pinout & Substrate Warning: In discrete TO-92 MOSFETs, the Bulk (substrate) is internally tied to the Source. However, in monolithic ICs like the ALD1102A (8-pin DIP), the substrate is a separate pin (Pin 8 for the NMOS pair). You must tie Pin 8 to the most negative potential in the circuit (Ground). If left floating or tied to a higher voltage, the parasitic substrate-to-source diodes will forward-bias, destroying the mirror and potentially the chip.

For the mirror to function accurately, the mirroring transistor (M2) must remain in the Saturation (Active) region. If M2 drops into the Triode region, the output current becomes dependent on the load voltage, ruining the constant-current behavior.

Table 2: MOSFET Operation Regions in a Current Mirror Context
Region Gate-Source (Vgs) Drain-Source (Vds) Drain Current (Id) Role in Current Mirror
Cutoff < Vgs(th) Any 0 A (leakage only) Off state; no mirroring occurs.
Triode (Linear) > Vgs(th) < Vgs - Vgs(th) Proportional to Vds Acts as a resistor; ruins mirror accuracy. M2 must avoid this.
Saturation > Vgs(th) ≥ Vgs - Vgs(th) Independent of Vds Required region. Id is controlled solely by Vgs, ensuring an accurate mirror.

Designing the Bias Network: A Complete Application Circuit

Let us design a precision 100 µA constant-current sink to bias a photodiode or low-current sensor using the ALD1102A NMOS pair. We will use a 12V DC supply (Vdd).

Component Selection and Math

  1. Reference Resistor (Rref): We need to set the reference current (Iref). The ALD1102A has a typical Vgs(th) of roughly 0.8V at low microamp currents. Assuming Vgs settles at 1.0V for our operating point, the voltage across Rref is Vdd - Vgs = 12V - 1.0V = 11.0V.
  2. Calculate Rref: R = V / I = 11.0V / 100µA = 110 kΩ. We will use a standard 110 kΩ 1% metal film resistor.
  3. Source Degeneration (Optional but recommended): To mitigate minor Vgs(th) mismatches and prevent thermal runaway, add source degeneration resistors (Rs1 and Rs2). A 100 Ω resistor in series with the source of both M1 and M2 introduces negative feedback. If M2 tries to draw more current, the voltage drop across Rs2 increases, effectively lowering its Vgs and throttling the current back down.
Channel Length Modulation (The Lambda Effect): In the real world, Id in saturation is not perfectly flat; it slopes upward slightly as Vds increases. If the voltage at M2's drain is vastly different from M1's drain (which is clamped to Vgs), the mirrored current will deviate. For high-precision requirements where the load voltage varies widely, upgrade this basic topology to a cascode current mirror or a Wilson current mirror to shield M2 from drain voltage variations. See the All About Circuits guide on MOSFET mirrors for cascode topology schematics.

Wiring the ALD1102A (8-Pin DIP)

  • Pin 1 (Drain 1): Connect to Rref (110k) and to Pin 3 (Gate 1).
  • Pin 2 (Source 1): Connect to Rs1 (100Ω), then to Ground.
  • Pin 3 (Gate 1): Tie to Pin 1 (Drain 1) and Pin 4 (Gate 2).
  • Pin 4 (Gate 2): Tie to Pin 3.
  • Pin 5 (Source 2): Connect to Rs2 (100Ω), then to Ground.
  • Pin 6 (Drain 2): Connect to your load (e.g., photodiode cathode). This is your 100 µA output.
  • Pin 7 (NC): No connection.
  • Pin 8 (Substrate): CRITICAL. Connect directly to Ground.

Failure Modes and Multimeter Diagnostics

MOSFETs are fragile, and current mirrors operate in regions where minor degradation causes massive output drift. Here is how these circuits fail in the wild and how to test them on your bench using a standard digital multimeter (DMM) like a Fluke 87V.

Common Failure Modes

  • Gate Oxide Puncture (ESD): The gate oxide layer in small-signal MOSFETs is incredibly thin. A static shock can punch a microscopic hole through it, creating a resistive short between the Gate and Source. The mirror will fail to bias, drawing massive current through Rref.
  • Thermal Runaway: If you use discrete FETs and physically separate them on a breadboard, M2 (which may be dissipating more heat if driving a heavy load) will warm up. As silicon heats up, Vgs(th) drops. M2 will draw more current, get hotter, and eventually destroy itself. Monolithic pairs (ALD1102A) prevent this because both dies share the exact same thermal mass.

Step-by-Step Multimeter Testing

If your current mirror is outputting 0mA or is pegged at the maximum supply current, follow this diagnostic sequence:

  1. De-energize and Isolate: Remove power. If possible, lift the Gate pins (Pins 3 and 4) out of the breadboard to isolate them from the rest of the circuit.
  2. Test for Gate Oxide Rupture: Set your DMM to Resistance mode (Auto-range). Measure between Gate (Pin 3/4) and Source (Pin 2/5). Expected: OL (Open Loop) or >10 MΩ. Failure: If you read anything under 1 MΩ, the gate oxide is punctured. Throw the IC away.
  3. Test the Body Diodes: Set your DMM to Diode Test mode. Place the Red probe on Source (Pin 2) and Black probe on Drain (Pin 1). Expected: ~0.4V to 0.6V (forward voltage of the parasitic body diode). Reverse the probes (Red on Drain, Black on Source). Expected: OL.
  4. Verify the Diode-Connection: In-circuit, measure the resistance of Rref. Ensure it hasn't drifted or opened. Measure the voltage across Rref while powered; if it reads exactly Vdd, M1 is shorted. If it reads 0V, M1 is open or Rref is open.

Monolithic Matched vs. Discrete: Which Should You Use?

When should you spend $2.50 on a matched pair versus $0.10 on discrete transistors? The decision comes down to the required precision and the operating environment.

Table 3: Monolithic Matched Pairs vs. Discrete MOSFETs
Criteria Monolithic Matched (e.g., ALD1102A) Discrete (e.g., 2x 2N7000)
Current Matching Accuracy Excellent (< 1% error at room temp) Poor (10% to 50% error typical)
Thermal Tracking d> Perfect (shared silicon die) None (requires manual thermal bonding)
Voltage Headroom Limited (typically 10V - 20V max Vds) High (60V+ easily available)
Current Capacity Low (usually < 50mA continuous) High (hundreds of mA to Amps)
Best Application Op-amp active loads, precision sensor bias, DACs High-power LED drivers, rough current limiting

For high-power applications where monolithic pairs cannot handle the current, you can still build a discrete current mirror, but you must add source degeneration resistors (as shown in the circuit above) and manually bin your discrete transistors. To bin discrete FETs, build a simple test jig with a fixed Vgs and measure Id for a batch of 20 transistors, selecting the two that read closest to each other. For a deeper dive into the semiconductor physics governing these mismatch errors, the MIT OpenCourseWare Microelectronic Devices curriculum provides excellent foundational models on channel length modulation and threshold variance.

By selecting the correct monolithic pair, respecting the substrate pinout, and keeping your mirroring FET firmly in the saturation region, you can build analog current sources that rival expensive bench equipment.