How to Read and Build a CMOS XOR Schematic for Digital Logic

A CMOS XOR schematic is the transistor-level blueprint showing how complementary PMOS pull-up and NMOS pull-down networks are arranged to output a logic HIGH only when its two inputs are at different voltage levels. In a real circuit or custom silicon layout, this specific schematic topology dictates the gate's propagation delay, dynamic power consumption, and physical silicon footprint. Beginners and hobbyists commonly confuse the standard static CMOS XOR layout with transmission-gate (pass-transistor) XOR schematics, or they mix up the XOR logic symbol with the XNOR (equivalence) symbol when reading datasheets.

The Transistor-Level Anatomy of a Static CMOS XOR

When you look at a textbook static CMOS XOR schematic, you are typically looking at a 12-transistor design. It consists of two main sections: the pull-up network (PUN) made of PMOS transistors, and the pull-down network (PDN) made of NMOS transistors. For the output to go HIGH, the PUN must connect the output to VCC while the PDN simultaneously disconnects it from GND. This only happens when Input A is HIGH and Input B is LOW, or vice versa.

The defining characteristic of the static CMOS schematic is that in any steady-state logic condition, there is never a direct DC path from VCC to GND. This means static power consumption is virtually zero, limited only by leakage current. Power is only consumed during the brief transition period when the inputs switch states and both networks are momentarily partially conductive.

Worked Numeric Example: Power and Delay in a 74HC86

Let us move from abstract schematics to a real-world bench measurement using the TI SN74HC86 quad 2-input XOR IC. Hobbyists often calculate power using the static quiescent current (Icc), but for CMOS logic switching at high frequencies, dynamic power dominates.

Dynamic power dissipation per gate is calculated using the power dissipation capacitance (Cpd) provided in the datasheet:

P = Cpd × Vcc² × f

• Cpd (Power Dissipation Capacitance): 22 pF (typical for 74HC86 at 5V)
• Vcc (Supply Voltage): 5.0 V
• f (Switching Frequency): 10 MHz (10,000,000 Hz)

Plugging in the numbers:

P = 22 × 10⁻¹² F × (5.0 V)² × 10,000,000 Hz
P = 22 × 10⁻¹² × 25 × 10⁷
P = 5.5 × 10⁻³ W, or 5.5 mW per gate.

If all four XOR gates in the 74HC86 package are toggling at 10 MHz, the total dynamic power is 22 mW. Add the quiescent power (roughly 20 µA × 5V = 0.1 mW), and your total package dissipation is roughly 22.1 mW. This numeric reality proves that at high frequencies, the switching capacitance of the CMOS schematic completely overshadows the static leakage current.

Where You Meet This in Practice

You will rarely build a CMOS XOR from discrete MOSFETs on a breadboard unless you are teaching a university semiconductor class. In practical electronics, the XOR schematic is implemented inside ICs or FPGAs for specific functional blocks:

• Phase Detectors in PLLs: An XOR gate acts as a simple phase detector. When two square waves of the same frequency are fed into the inputs, the duty cycle of the output pulse is directly proportional to the phase difference between the inputs. This DC average is filtered to lock a VCO.
• Parity Generators and Checkers: Cascading XOR gates allows you to count the number of HIGH bits in a data bus. If the final output is HIGH, you have an odd number of 1s (odd parity), which is foundational for error detection in UART and memory systems.
• Half-Adders: In arithmetic logic units (ALUs), the XOR gate generates the 'Sum' bit of a single-bit addition, while an AND gate generates the 'Carry' bit.
• Quadrature Encoders: XOR gates are used to multiply the frequency of rotary encoder signals or to detect the direction of rotation by comparing the phase of the A and B channels.

Decision Tree: Picking Your XOR Implementation

Do not default to the first logic chip you find in your parts bin. Use this decision matrix to select the exact architecture and part number for your project.

Default Recommendation: If you are building a general-purpose DIY digital logic project on a breadboard and have a standard 5V supply, buy the SN74HC86. It offers the best balance of propagation delay (typically 14 ns at 5V), drive strength, and availability.

Common Schematic Mistakes and How to Avoid Them

Even with the right IC, poor schematic and layout practices will ruin your XOR gate performance. Watch out for these specific failure modes:

1. Floating Inputs: CMOS inputs have incredibly high impedance. If you leave an unused XOR input unconnected, it will act as an antenna, pick up environmental noise, and cause the internal PMOS and NMOS networks to switch erratically. This creates massive shoot-through current that can physically melt the silicon die. Fix: Always tie unused inputs to VCC or GND via a 10kΩ resistor.
2. Missing Decoupling Capacitors: Because CMOS gates draw a sharp spike of current from the power rail during the nanosecond they switch states, a lack of local bypass capacitance will cause VCC droop. Fix: Place a 100 nF MLCC capacitor as close to the VCC and GND pins of the XOR IC as physically possible.
3. Confusing XOR with XNOR: The schematic symbol for XOR has a single curved line near the inputs. The XNOR (Exclusive-NOR) has that same curved line, plus an inversion bubble on the output. If your circuit requires a HIGH output when inputs match, and you wire an XOR, your logic will be entirely inverted. Fix: Verify the truth table in the datasheet before wiring the board.

FAQ: CMOS XOR Schematic Questions