Anatomy of a Class D Power Amplifier Circuit Diagram
If you are transitioning from linear audio design to switching topologies, reading a class D power amplifier circuit diagram for the first time can feel like looking at a switch-mode power supply rather than an audio amplifier. That is because, fundamentally, it is a power supply whose output voltage is modulated by an audio signal.
Unlike a Class AB amplifier where the output transistors operate in their linear (active) region and dissipate massive amounts of heat, a Class D topology switches the output MOSFETs fully on and fully off. This yields efficiencies north of 90%, eliminating the need for massive heat sinks. For a deep dive into the theoretical efficiency differences, the Analog Devices technical library on Class D audio amplifiers provides excellent baseline math.
Node Labels and Topology Flow
A standard discrete Class D topology consists of four distinct stages. Here are the critical nodes you will see on the schematic:
- $V_{in}$ (Audio Input): The low-voltage AC audio signal, typically centered around a DC bias midpoint.
- $V_{tri}$ (Carrier Wave): A high-frequency triangle or sawtooth wave (typically 200kHz to 500kHz) generated by an oscillator.
- $V_{pwm}$ (Modulated Logic): The output of the comparator, where $V_{in}$ and $V_{tri}$ intersect to create a variable duty-cycle square wave.
- $V_{gate\_H}$ / $V_{gate\_L}$ (Gate Drive): The high-side and low-side drive signals, featuring a critical "dead-time" gap to prevent shoot-through.
- $V_{sw}$ (Switch Node): The junction between the high-side and low-side MOSFETs. This node violently swings between ground and the bus voltage ($V_{bus}$).
- $V_{out}$ (Filtered Output): The node after the LC low-pass filter, where the high-frequency carrier is stripped away, leaving only the amplified audio.
Design Walkthrough: Picking Real Component Values
Let us walk through a practical, 15W educational discrete Class D design running on a 24V $V_{bus}$. We will avoid integrated black-box chips like the TPA3116D2 here so you can actually see the circuit behavior.
1. Carrier and Modulator Stage
We use an NE555 timer in astable mode to generate a 250kHz triangle wave ($V_{tri}$). Set R1 = 1kΩ, R2 = 10kΩ, and C = 1nF. Feed this into the non-inverting input of an LM393 comparator. Feed your audio signal ($V_{in}$) into the inverting input via a 10kΩ volume potentiometer. Critical detail: The LM393 has an open-collector output. You must add a 10kΩ pull-up resistor to 5V on the comparator output to get a valid $V_{pwm}$ logic signal.
2. Gate Driver and Power Stage
The $V_{pwm}$ signal feeds into an IR2110 half-bridge gate driver. The IR2110 requires a 12V logic supply (VCC) and handles the high-side bootstrap via a 1µF ceramic capacitor and a UF4007 diode. The power stage uses two IRFZ44N N-channel MOSFETs. N-channel MOSFETs are preferred over P-channel for the high side due to lower $R_{DS(on)}$ and faster switching speeds, which is why the IR2110 includes a charge pump to drive the high-side gate above $V_{bus}$.
3. LC Output Filter
The $V_{sw}$ node outputs a 24V peak-to-peak PWM square wave. We need to strip the 250kHz carrier and pass the 20Hz-20kHz audio. We use a second-order Butterworth LC low-pass filter. For an 8Ω load and a 30kHz cutoff frequency, the math dictates an inductor (L) of roughly 33µH and a capacitor (C) of 680nF. Use a powdered-iron toroidal inductor to prevent saturation, and a polypropylene film capacitor for C.
Behavior Matrix and Extreme Failure Modes
Understanding how component drift or failure affects the switch node ($V_{sw}$) is crucial for debugging. Here is what happens when key elements change or fail.
| Component Modified / Failed | Parameter Changed | Effect on Switch Node ($V_{sw}$) | Effect on Audio Output ($V_{out}$) |
|---|---|---|---|
| LM393 Pull-up Resistor | Increased from 10kΩ to 100kΩ | Rise time of $V_{pwm}$ slows down; high-side MOSFET turns on sluggishly. | Increased high-frequency hiss; MOSFETs run hot due to linear-region crossover. |
| Bootstrap Capacitor | Decreased from 1µF to 0.1µF | High-side gate voltage sags during long high-duty cycles. | Bass frequencies (long high-side ON times) distort heavily or cut out completely. |
| Output Inductor (L) | Core saturates (e.g., wrong material) | Current spikes violently during MOSFET turn-on; massive ringing on $V_{sw}$. | Harsh clipping, potential MOSFET destruction from over-current. |
| High-Side MOSFET Short | Drain-Source shorted | $V_{sw}$ clamps permanently to $V_{bus}$ (24V). | Massive DC offset hits speaker. Voice coil burns open. Low-side MOSFET explodes if it tries to turn on. |
| Bootstrap Diode Open | Diode fails open circuit | High-side gate floats; only low-side MOSFET switches. | Half-wave rectified audio. Severe distortion, massive DC current through speaker. |
Step-by-Step Breadboard Testing Protocol
Let us address a common bench mistake: you cannot build the 24V half-bridge power stage of a Class D amplifier directly on a cheap solderless breadboard. The contact strips introduce 10nH to 20nH of parasitic inductance. When the MOSFETs switch at 250kHz with high $di/dt$, the formula $V = L(di/dt)$ generates massive voltage spikes that will ring past the MOSFET's $V_{GS}$ max and destroy the gates. You must build the power stage on a copper-clad perfboard with short, thick leads. However, you can and should breadboard the logic stages first.
- Stage 1: PWM Logic Verification (5V). Build only the NE555 triangle generator and the LM393 comparator on the breadboard. Power with 5V. Connect an oscilloscope to the $V_{tri}$ node to verify a clean 250kHz triangle wave. Inject a 1kHz sine wave from a function generator into $V_{in}$. Probe $V_{pwm}$ and verify the duty cycle widens and narrows in sync with the audio sine wave.
- Stage 2: Gate Drive Verification (12V). Add the IR2110 to the breadboard. Connect VCC to 12V, but do not connect the high-voltage bus ($V_{bus}$) or the MOSFETs yet. Probe the $V_{gate\_H}$ and $V_{gate\_L}$ pins. You should see clean 12V square waves. Crucially, zoom in on the transitions to verify there is a "dead-time" (a brief period where both gates are low) to prevent shoot-through. The IR2110 has built-in dead-time, but verify it is at least 100ns.
- Stage 3: Low-Side Dummy Load Test. Move to your perfboard for the power stage. Solder the IRFZ44N MOSFETs and the LC filter. For the first power-on, disconnect the high-side MOSFET entirely. Connect a 10Ω, 10W power resistor as a dummy load instead of a speaker. Apply 12V to $V_{bus}$. Probe $V_{sw}$. It should swing cleanly between 0V and 12V without massive ringing. If you see 30V spikes, your layout parasitics are too high; add an RC snubber (e.g., 10Ω + 4.7nF) across the low-side MOSFET.
- Stage 4: Full Bridge Integration. Install the high-side MOSFET. Keep the dummy load connected. Slowly ramp $V_{bus}$ from 12V up to 24V while monitoring the temperature of the MOSFETs. If they stay cool, replace the dummy load with an 8Ω speaker and inject real audio.
Frequently Asked Questions
Why does my class D power amplifier circuit diagram need a dead-time generator?
Dead-time is a mandatory microsecond-scale delay inserted between the turn-off of one MOSFET and the turn-on of the other. MOSFETs turn off slower than they turn on due to the Miller effect and gate discharge characteristics. If the PWM logic commands the high-side to turn on at the exact same moment the low-side turns off, both will conduct simultaneously for a few nanoseconds. This creates a direct short from $V_{bus}$ to ground (shoot-through), resulting in massive current spikes, electromagnetic interference (EMI), and eventual thermal destruction of the MOSFETs.
Can I use a standard electrolytic capacitor for the Class D output filter?
No. The LC output filter must handle high-frequency ripple current (at the 250kHz+ switching frequency) superimposed on the audio signal. Standard aluminum electrolytic capacitors have high Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) at these frequencies. They will overheat, fail prematurely, and cause severe high-frequency distortion. Always use low-ESR polypropylene film capacitors or high-frequency ceramic (X7R/C0G) capacitors for the Class D output filter.
How do I calculate the LC filter values for a 4-ohm speaker?
The LC filter cutoff frequency ($f_c$) should typically be placed between 25kHz and 35kHz—well above the 20kHz audio band, but well below the switching frequency to ensure adequate carrier attenuation. The formula for the inductor is $L = R_{load} / (2 \pi f_c)$ and for the capacitor is $C = 1 / (2 \pi f_c R_{load})$. For a 4Ω speaker and a 30kHz target cutoff: $L = 4 / (2 \pi \times 30000) \approx 21.2\mu H$, and $C = 1 / (2 \pi \times 30000 \times 4) \approx 1.32\mu F$. Always select the nearest standard component values and verify the inductor's saturation current rating exceeds your maximum load current.
What causes high-frequency hiss in a DIY Class D amplifier?
High-frequency hiss or a "fizzy" top-end in a discrete Class D build usually stems from three culprits. First, inadequate dead-time causing micro-shoot-through spikes that radiate as EMI. Second, a poor PCB or perfboard layout where the high-current switching loop (from $V_{bus}$ decoupling caps, through the MOSFETs, and back to ground) is too large, acting as an antenna. Third, using a comparator with a slow slew rate or inadequate pull-up, resulting in jitter on the PWM edges. For comprehensive layout guidelines, refer to the Texas Instruments speaker amplifier design resources, which detail strict grounding and decoupling practices for switching audio stages.
