A ckt diagram of power supply (circuit diagram) is the schematic blueprint that maps the conversion of raw input voltage to a regulated, stable output. The direct answer to choosing a topology depends on your load: for a 12V input to 5V/2A load, a switching buck converter (like the TI TPS5430) is the standard choice, yielding ~85% efficiency and minimal heat. A linear regulator (LDO) in the same scenario drops to ~41% efficiency and dissipates 14W of heat, requiring massive heatsinks. Below, we break down the topology math, input protection, and a complete 12V-to-5V design example.
Linear vs. Switching: Choosing the Right Topology
When reviewing a ckt diagram of power supply, the first major branch is linear versus switching. Linear regulators act as variable resistors, burning excess voltage as heat. Switching regulators use high-frequency pulse-width modulation (PWM) and energy storage elements (inductors/capacitors) to transfer power efficiently.
| Parameter | Linear (LDO) | Switching (Buck) |
|---|---|---|
| Efficiency | 41.6% ($V_{out}/V_{in}$) | 85% - 92% |
| Heat Dissipation | 14.0W ($(12V-5V) \times 2A$) | 1.1W - 1.8W |
| Output Noise / Ripple | < 1mV RMS (Ultra-low) | 20mV - 50mV p-p (Switching noise) |
| Component Cost & BOM | Low ($0.50 - $1.50, 3 pins) | Medium ($3.00 - $6.00, 10+ components) |
| Transient Response | Excellent (kHz to MHz bandwidth) | Good (Limited by LC filter resonance) |
The Verdict: Choose linear only when your dropout voltage is minimal (e.g., 5.5V to 5.0V), your current draw is under 100mA, or you are powering ultra-sensitive RF/ADC circuitry where switching noise is unacceptable. For almost all 12V-to-5V, 24V-to-12V, or battery-fed logic rails, switching is mandatory to prevent thermal runaway.
Anatomy of a 12V-to-5V Switching CKT Diagram
Let’s design a robust 12V nominal (9V–16V range) to 5V @ 3A continuous buck converter. This is a common requirement for powering embedded systems (like a Raspberry Pi or ESP32 cluster) from a 12V sealed lead-acid battery or industrial DC bus.
Input Range and Protection Stage
A raw 12V bus is noisy and prone to transients. Your ckt diagram must include front-end protection before the regulator:
- Transient Voltage Suppression (TVS): A unidirectional TVS diode like the SMAJ15A clamps inductive spikes (load dump) to 15V, protecting downstream silicon.
- Overcurrent Protection: A 5A PTC resettable polyfuse limits current during a dead short.
- Reverse Polarity: Instead of a diode (which drops 0.5V and wastes heat), use a P-channel MOSFET (e.g., SI2301) configured as an ideal diode. It blocks reverse current with a voltage drop of merely $I^2R$ (typically <20mV at 3A).
Regulator and Power Stage Specs
For the core conversion, we will use the Texas Instruments TPS5430, a 5.5V to 36V input, 3A output step-down converter.
| Component | Reference Designator | Value / Part Number | Purpose |
|---|---|---|---|
| Buck Controller IC | U1 | TPS5430DDA | 500kHz PWM switching controller |
| Power Inductor | L1 | 10µH (Wurth 744774210) | Energy storage, rated for 4A saturation |
| Catch Diode | D1 | SS34 (Schottky, 40V/3A) | Freewheeling path during off-time |
| Input Capacitor | C1, C2 | 10µF X7R Ceramic (x2) | High-frequency RMS ripple handling |
| Output Capacitor | C3 | 220µF Low-ESR Electrolytic + 100nF Ceramic | Bulk storage and high-freq decoupling |
| Feedback Resistors | R1, R2 | 10kΩ and 3.24kΩ (1%) | Sets $V_{out}$ to exactly 5.0V |
Ripple and Noise Expectations
With a 10µH inductor and 500kHz switching frequency, the inductor ripple current ($\Delta I_L$) is roughly 0.6A. The output voltage ripple is dominated by the capacitor's Equivalent Series Resistance (ESR). Using a low-ESR Panasonic FR series electrolytic (ESR ~0.08Ω) combined with a 100nF ceramic bypass, you should measure 25mV to 35mV peak-to-peak ripple on an oscilloscope using a tip-and-barrel probe. If you see 200mV+ of ringing, your probe ground lead is acting as an antenna; do not blame the circuit.
Thermal Derating and Headroom Math
You cannot select a regulator without proving it will survive your worst-case operating conditions. Let's look at the math that separates a working prototype from a melted field unit.
Dropout and Headroom (Why Linear Fails Here)
Suppose you tried to use a popular linear regulator, the LM1085 (3A LDO), to drop a 12V battery to 5V. The datasheet specifies a maximum dropout voltage ($V_{DO}$) of 1.5V at 3A. The headroom rule dictates:
$$V_{in(min)} \ge V_{out} + V_{DO}$$
$$V_{in(min)} \ge 5.0V + 1.5V = 6.5V$$
If your 12V lead-acid battery sags to 6.0V under a heavy cranking load, the LDO drops out of regulation. Your 5V rail collapses to 4.5V, triggering a brownout reset on your microcontroller. A switching buck converter, however, can maintain 5V output even if the input sags to 5.5V (accounting for MOSFET $R_{DS(on)}$ and inductor DCR losses), making it vastly superior for battery-fed systems.
Thermal Derating Calculation
For our TPS5430 switching design, total power dissipation ($P_{loss}$) at 3A is approximately 0.85W (accounting for conduction, switching, and gate drive losses). The TPS5430DDA package has a junction-to-ambient thermal resistance ($\theta_{JA}$) of roughly 40°C/W when soldered to a standard 2-layer PCB with moderate copper pours.
$$\Delta T = P_{loss} \times \theta_{JA} = 0.85W \times 40°C/W = 34°C$$
At a standard 25°C ambient room temperature, the silicon junction ($T_J$) sits at 59°C—well below the 125°C thermal shutdown threshold. However, if this board is mounted inside a sealed outdoor enclosure where ambient reaches 65°C, $T_J$ climbs to 99°C. While still technically functional, electrolytic capacitor lifespan halves for every 10°C rise. Derating action: Increase the bottom-layer copper pour area beneath the IC's thermal pad to drop $\theta_{JA}$ to 25°C/W, or switch to an all-ceramic output capacitor design to eliminate heat-sensitive electrolytics.
Power Supply Circuit FAQs
How do I calculate the inductor value in a buck ckt diagram?
The inductor value dictates your ripple current. The standard formula is $L = \frac{V_{out} \times (V_{in} - V_{out})}{V_{in} \times f_{sw} \times \Delta I_L}$. For a 12V to 5V conversion at 500kHz, targeting a ripple current ($\Delta I_L$) of 30% of your max load (e.g., 0.9A for a 3A load), the math yields $L = 6.48\mu H$. You then select the next standard value up—typically 6.8µH or 10µH. Choosing a slightly higher inductance (10µH) reduces ripple current and output voltage ripple, at the cost of slightly slower transient response.
What input protection is mandatory for a 24V industrial ckt diagram?
Industrial 24V PLC buses are notoriously harsh. Your ckt diagram must include a bidirectional TVS diode (like the SMAJ24CA) to clamp both positive and negative transients. You must also include a common-mode choke (e.g., Wurth WE-CMB) to filter out high-frequency EMI generated by adjacent motor drives. Finally, an Over-Voltage Protection (OVP) crowbar circuit or a dedicated OVP IC (like the TI TPS2596) is required to physically disconnect the load if the 24V bus accidentally spikes above 30V, which would instantly destroy standard 5V logic.
Why does my linear power supply ckt diagram oscillate under load?
Oscillation (often seen as low-frequency ringing on the output) in a linear regulator ckt diagram is almost always caused by incorrect output capacitor Equivalent Series Resistance (ESR). Older LDOs (like the LM317 or LM1085) require a minimum ESR (typically 0.1Ω to 1.0Ω) to maintain phase margin in their internal compensation loop. If you use a modern, ultra-low ESR ceramic capacitor (ESR < 0.01Ω) on an LDO designed for tantalum or electrolytic caps, the phase margin drops to zero, and the regulator turns into an oscillator. Always check the datasheet's "Output Capacitor Requirements" graph before swapping cap chemistries.
