If you are asking what is circuit switched data, the answer depends on whether you are looking at a telecom specification or a physical PCB layout. In telecommunications, Circuit-Switched Data (CSD) refers to the legacy GSM protocol that established a dedicated, continuous physical radio channel for data transmission. But in hardware design and bench electronics, circuit-switched data routing refers to establishing an exclusive, low-latency physical electrical path between a specific input node and output node using crosspoint switches or multiplexers. Unlike packet-switched or shared-bus topologies (like I2C, SPI, or Ethernet) where data is broken into chunks and routed over a common wire, a circuit-switched hardware topology physically connects Node A to Node B, isolating it from all other network traffic for the duration of the session.

When you design a circuit-switched matrix, the switch itself is the circuit. This guide walks through designing a physical 4x4 circuit-switched data routing matrix, selecting real component values, and testing the failure modes on the bench.

Circuit-Switched vs. Shared-Bus Hardware Topologies

Why choose a dedicated circuit-switched topology over a shared packet-switched bus? The decision comes down to signal integrity, latency, and analog compatibility. Shared buses require protocol overhead, packetization, and arbitration. If a node hogs the bus, others wait. A circuit-switched matrix, built with analog crosspoint switches, routes raw signals (digital or analog) without protocol overhead. Once the path is closed, the bandwidth is guaranteed and the latency is limited only by the propagation delay of the silicon.

Criteria Circuit-Switched Matrix (Crosspoint) Shared-Bus (Packet/Message Switched)
Latency Deterministic (ns to μs range, based on Ron and Cload) Variable (requires arbitration, packet headers, ACKs)
Signal Type Routes raw analog or digital waveforms transparently Strictly digital, protocol-bound (e.g., I2C, CAN)
Isolation High (Off-isolation typically -60dB to -90dB) Low (all nodes share the same physical trace capacitance)
Component Count Higher (requires dedicated crosspoint ICs per node cluster) Lower (simple pull-ups, shared traces, transceivers)
Bench Tip: Use circuit-switched routing when you need to multiplex high-speed analog signals (like audio or sensor arrays) or when you need to guarantee that a critical digital interrupt line has a dedicated, un-arbitrated path to a microcontroller GPIO.

Designing a 4x4 Circuit-Switched Data Matrix

To build a physical layer circuit-switched matrix, we will use the Analog Devices ADG2128, a 4x4 analog crosspoint switch. This IC provides 16 independent switch elements arranged in a matrix. The control plane uses I2C (packet-switched) to configure the switches, but the data plane is purely circuit-switched.

Topology and Node Labels

The topology consists of four input lines labeled X0 through X3 and four output lines labeled Y0 through Y3. Any X node can be connected to any Y node. Multiple X nodes can connect to a single Y node (acting as a multiplexer), but connecting multiple X nodes to the same Y node simultaneously will short those inputs together if they are driven by low-impedance sources.

Component Specification Sheet

Before wiring the breadboard, review the critical silicon parameters that dictate your signal limits. These values assume a 3.3V logic supply and a 5V analog supply.

Parameter ADG2128 Typical Value Design Implication
Analog Supply (VDD) 3.0V to 16.5V Allows routing of ±5V analog signals if using dual supplies.
On-Resistance (Ron) 300 Ω (typical at 5V) Forms an RC low-pass filter with load capacitance; limits high-frequency bandwidth.
-3dB Bandwidth 600 MHz More than sufficient for digital logic and audio, but watch for reflections at RF.
t_ON / t_OFF 1.5 μs / 1.0 μs Switching speed limit; do not use for sub-microsecond PWM routing.
Charge Injection (Qinj) 15 pC Causes voltage spikes on high-impedance loads when the switch toggles.

Design Walkthrough: Picking Real Component Values

A crosspoint switch is only as stable as its power delivery and control lines. Here is the exact bill of materials and configuration for a robust 3.3V digital routing matrix:

  • Decoupling: Place a 100nF X7R ceramic capacitor and a 10μF tantalum capacitor as close to the VDD and GND pins of the ADG2128 as physically possible. Crosspoint matrices draw sharp current spikes during simultaneous switch transitions.
  • I2C Pull-ups: The I2C control lines (SDA, SCL) require 4.7kΩ pull-up resistors to the 3.3V logic rail. Do not rely on internal microcontroller pull-ups; their high resistance (often 20kΩ-50kΩ) will result in slow rise times and I2C bus timeouts.
  • Address Pins: Tie the A0 and A1 pins directly to GND for a base I2C address of 0x71. Use 10kΩ pull-down resistors if you need to hardwire them but want to maintain the option to cut a trace and re-address later.

Failure Modes: What Breaks at the Extremes?

Understanding what happens when a circuit-switched element fails is critical. Unlike a shared bus where a single short can pull the entire network down, a matrix localizes failures, but introduces new risks like charge injection and bus contention.

Behavior Table: Element Changes and Faults

Element Changed / Fault Condition Effect on Target Output Node (e.g., Y0) Effect on VCC / System
Switch X0-Y0 Closes (Normal) Y0 assumes X0 voltage minus I×Ron drop. Transient current spike (~2mA) as gate capacitance charges.
Switch X0-Y0 Opens (Normal) Y0 floats; voltage decays based on load capacitance. Charge injection dumps ~15pC into Y0, causing a brief mV spike.
X0 Shorts to VCC externally If X0-Y0 is closed, Y0 is pulled to VCC. If open, Y0 is isolated. Current limited only by the X0 driver; ADG2128 internal ESD diodes may conduct if VCC is exceeded.
X0 and X1 both close to Y0 Y0 voltage becomes the averaged/contested voltage of X0 and X1. Cross-current flows from X0 through the matrix to X1. Can exceed 30mA and thermally damage the silicon.

What Breaks at the Extremes?

The Open Extreme: If a switch element fails open internally (a rare silicon defect), the node simply floats. In high-impedance analog circuits, a floating Y node will act as an antenna, picking up 50/60Hz mains hum. Always place a 100kΩ pull-down resistor on every Y output node to define a known state when all switches are open.

The Short Extreme: The most catastrophic failure in a circuit-switched matrix is bus contention. If your firmware accidentally commands the ADG2128 to close both X0-Y0 and X1-Y0, and both X0 and X1 are driven by push-pull microcontroller GPIOs outputting opposite logic levels (one HIGH, one LOW), you have created a dead short through the 300Ω Ron switches. The current will be (3.3V - 0V) / (300Ω + 300Ω) = 5.5mA. While 5.5mA won't instantly melt the ADG2128 (it handles up to 30mA continuous), doing this across multiple nodes simultaneously will trigger thermal shutdown or permanently degrade the Ron specification of the CMOS transistors.

Breadboard Testing and Verification Steps

Do not trust the datasheet blindly; verify the physical layer. Here is how to breadboard and test your circuit-switched data matrix step-by-step using a standard multimeter and an oscilloscope.

Safety Callout: This procedure uses low-voltage DC (3.3V/5V). However, if you adapt this topology for mains-rated relays or high-voltage analog multiplexing, always de-energize the board, lock out the power supply, and verify dead with a tested CAT III meter before probing.
  1. Verify Power Rails Before Inserting the IC: Power your breadboard without the ADG2128 installed. Use your multimeter to measure between the VDD and GND rails. You must read 3.3V ± 5% (3.13V to 3.46V). If it reads 5V, your LDO is misconfigured and you will fry the I2C logic of the switch.
  2. Check I2C Idle State: With the pull-up resistors installed, probe SDA and SCL. Both should read a steady 3.3V DC. If either reads 0V, you have a short to ground or a misconfigured microcontroller GPIO holding the line low.
  3. Measure Off-Isolation (The Open Test): Seat the IC. Program your microcontroller to ensure all switches are OPEN. Apply a 1kHz, 1Vpp sine wave to X0. Probe Y0 with an oscilloscope. The signal should be buried in the noise floor (typically < 1mVpp), confirming the -60dB off-isolation spec. If you see a clean sine wave, your I2C commands are failing and the switch is defaulting to a closed state.
  4. Measure Ron Voltage Drop (The Closed Test): Command the X0-Y0 switch to CLOSE. Apply a steady 3.3V DC to X0. Connect a 1kΩ load resistor from Y0 to GND. Measure the voltage at Y0. It should read approximately 2.51V. Calculation: The 300Ω Ron and 1kΩ load form a voltage divider: 3.3V * (1000 / 1300) = 2.53V. If it reads significantly lower, your switch element is damaged or your VDD is sagging under load.
  5. Test Charge Injection: Set your oscilloscope to AC coupling, 10mV/div, and single-trigger mode. Probe Y0 (with a 10kΩ pull-down). Command the X0-Y0 switch to toggle rapidly. You will see a sharp, narrow voltage spike on the scope exactly at the moment of transition. Measure the peak-to-peak amplitude of this spike to quantify the charge injection in your specific layout.

By treating circuit-switched data not just as a telecom legacy term, but as a rigorous physical routing architecture, you eliminate bus arbitration delays and guarantee signal isolation. Whether you are routing precision analog sensor data or creating a fault-tolerant digital redundancy matrix, the crosspoint topology provides a deterministic, hardware-level solution that shared buses simply cannot match.