If you want to know how to check a capacitor on a circuit board accurately, you must first accept a harsh reality of PCB diagnostics: standard DC multimeters and low-frequency LCR meters are virtually useless for in-circuit testing. Parallel copper traces, semiconductor junctions, and adjacent passive components create complex impedance networks that mask the true health of the Device Under Test (DUT). To check a capacitor while it is still soldered to the board, you must use a High-Frequency AC Injection Topology. By injecting a low-voltage, high-frequency signal (typically 100 kHz), you force the capacitive reactance near zero, isolate the Equivalent Series Resistance (ESR), and keep parallel silicon junctions from turning on.
The 100 kHz In-Circuit Injection Topology
The core of any professional in-circuit capacitor tester relies on a specific AC injection topology. The goal is to measure the ESR and gross capacitance without triggering parallel diodes or transistor base-emitter junctions, which typically turn on at 0.6V. By keeping the injection amplitude below 200 mV peak-to-peak and pushing the frequency to 100 kHz, the capacitive reactance ($X_c$) of most board-level decoupling and filter capacitors (>1 µF) drops below 1 Ω. At this point, the impedance you measure is almost entirely the ESR.
Node Map:
- Node 1 (Injection Source): The output of the 100 kHz oscillator, fed through a precision source resistor ($R_s$).
- Node 2 (Sense / DUT-High): The junction between $R_s$ and the positive terminal of the capacitor. This is where the voltage drop is measured.
- Node 3 (Return / DUT-Low): The ground reference, connected to the negative terminal of the capacitor.
Here is the exact component specification for designing a bench-top diagnostic jig based on this topology. These values are optimized for checking electrolytic and tantalum capacitors in the 10 µF to 1000 µF range.
| Parameter | Component / Value | Tolerance / Spec | Purpose in Topology |
|---|---|---|---|
| Injection Frequency | 100 kHz Square Wave | ±1% stability | Minimizes $X_c$ to < 1 Ω for caps > 3 µF |
| Source Resistor ($R_s$) | 50 Ω Metal Film | 1%, 1/4W | Creates a known voltage divider with DUT ESR |
| Injection Amplitude | 100 mV RMS (282 mV pk-pk) | Clipped / Regulated | Prevents forward-biasing parallel PN junctions |
| Sense Amplifier Gain | 100x (Non-inverting Op-Amp) | Bandwidth > 1 MHz | Boosts the millivolt-level Node 2 signal for ADC/Scope |
| Max Node 2 Voltage | < 200 mV pk-pk | Hard limit | Ensures parallel silicon remains reverse-biased/off |
Transient & Steady-State Behavior Matrix
When probing Node 2 on the board, you are looking at the AC voltage drop across the capacitor's internal ESR. Because $V_{node2} = V_{inject} \times (Z_{DUT} / (R_s + Z_{DUT}))$, any change in the capacitor's health drastically alters the waveform at Node 2. Below is the behavior matrix detailing what happens at the extremes and during typical failure modes.
| DUT Condition | Node 2 AC Voltage (Approx) | Phase Shift vs Node 1 | Physical Meaning & Board Impact |
|---|---|---|---|
| Healthy (Low ESR) | < 5 mV pk-pk | Near 0° (Resistive) | $X_c$ and ESR are minimal; cap is filtering correctly. |
| High ESR (Dried Out) | 15 mV - 80 mV pk-pk | Near 0° (Resistive) | Electrolyte has boiled off; ESR dominates impedance. Fails under ripple load. |
| Shorted (Extreme) | 0 mV (Flatline) | N/A | Dielectric breakdown. Node 2 is pulled directly to Node 3 (Ground). |
| Open (Extreme) | ~282 mV pk-pk (Full Scale) | -90° (Capacitive) | Internal tab断裂 (broken). $Z_{DUT}$ is infinite; no current flows through $R_s$. |
| Parallel Diode Present | Clipped / Distorted | Non-linear | Injection voltage exceeded 0.6V; topology design failed or DUT is open. |
Why High-Frequency Injection Over DC or Low-Freq LCR?
You might wonder why you cannot simply use a standard multimeter's capacitance range or a benchtop LCR meter set to 1 kHz. The answer lies in parallel circuit paths. According to Keysight's Impedance Measurement Handbook, in-circuit measurements are severely compromised by parallel components.
If you apply a DC voltage (like a multimeter's ohms range), you will simply charge the capacitor and read the leakage current of parallel ICs, eventually showing an 'Open' or 'OL' regardless of the capacitor's actual ESR. If you use a low-frequency AC signal (100 Hz or 1 kHz), the capacitive reactance ($X_c$) remains high enough that parallel inductors, ferrite beads, and low-impedance power planes will shunt your test signal away from the DUT. Furthermore, a standard LCR meter often outputs 1V to 2V RMS. On a populated board, 1V RMS is enough to forward-bias parallel protection diodes and transistor junctions, completely invalidating the reading. The 100 kHz / 100 mV topology is the only reliable way to check a capacitor on a circuit board without lifting a leg.
Step-by-Step: Breadboarding the Diagnostic Jig
Before probing a live or depopulated board, it is best practice to breadboard the injection topology to verify your sense amplifier and oscillator. Here is how to build a functional 100 kHz diagnostic jig using discrete logic.
- Build the Astable Oscillator: Use a 74HC14 hex Schmitt-trigger inverter. Connect a 1 kΩ resistor and an 8.2 nF ceramic capacitor between the input and output of the first gate to create an astable multivibrator. This yields a square wave at approximately 105 kHz ($f \approx 1 / (1.2 \times R \times C)$).
- Buffer the Signal: Route the oscillator output through a second 74HC14 gate to buffer the signal and sharpen the edges.
- Attenuate to 100 mV: Build a voltage divider using a 4.7 kΩ and a 100 Ω resistor to drop the 5V logic-level square wave down to roughly 100 mV pk-pk.
- Inject the Source Resistor: Solder a precision 50 Ω metal film resistor to the attenuated output. The free end of this resistor is your Node 1 injection point.
- Connect the DUT: Clip your test leads to the capacitor. Connect the positive lead to Node 1 (which becomes Node 2 at the junction) and the negative lead to circuit ground (Node 3).
- Measure Node 2: Connect an oscilloscope probe to Node 2. Set the scope to AC coupling, 10 mV/div, and 5 µs/div. A healthy 100 µF electrolytic will show a flatline near 0 mV. A degraded cap will show a distinct square wave measuring 20+ mV pk-pk.
The In-Circuit Reality: MLCCs and Edge Cases
While the 100 kHz topology is the gold standard for checking electrolytic and tantalum capacitors on a circuit board, it hits a physical wall with Multi-Layer Ceramic Capacitors (MLCCs). As noted in Texas Instruments' capacitor application guides, MLCCs used for high-frequency decoupling (e.g., 100 nF / 0.1 µF) have a much higher reactance at 100 kHz.
For a 100 nF MLCC, $X_c$ at 100 kHz is roughly 15.9 Ω. Because this is no longer negligible compared to the 50 Ω source resistor, the voltage at Node 2 will be elevated even on a perfectly healthy ceramic capacitor. To check small MLCCs in-circuit, professional ESR meters push the injection frequency up to 1 MHz or use a resonant LC tank topology to measure the Q-factor rather than raw ESR.
By understanding the impedance relationships at high frequencies, you can stop guessing and start measuring. The 100 kHz injection topology turns a complex, parallel-laden PCB into a simple voltage divider, allowing you to confidently check a capacitor on a circuit board and identify dried-out electrolytics before they cause catastrophic power rail collapse.
