Putting amplifiers in series—technically known as cascading—means routing the output of one amplification stage directly into the input of the next. In a cascaded topology, the total voltage gain is the product of the individual stage gains ($A_{V(total)} = A_{V1} \times A_{V2}$). While it might seem simpler to use a single amplifier with massive gain, real-world physics and semiconductor limits force us to chain stages together to achieve high gain without sacrificing bandwidth or stability.
Topology and Node Labels: Why Cascade?
To understand signal flow, we map the circuit into three distinct nodes:
- Node A (Vin): The input signal enters the non-inverting input of Stage 1.
- Node B (Interstage): The output of Stage 1 connects directly to the non-inverting input of Stage 2. This node carries the interstage signal.
- Node C (Vout): The output of Stage 2 drives the final load or measurement equipment.
Why Series Over a Single High-Gain Stage?
The primary reason to cascade amplifiers in series is the Gain-Bandwidth Product (GBWP) limit. Every operational amplifier has a fixed GBWP. If you use a single Texas Instruments NE5532 (which has a typical GBWP of 10 MHz) and configure it for a gain of 1,000 (60 dB), your usable bandwidth shrinks to just 10 kHz. That is entirely inadequate for high-fidelity audio or fast transient signals.
By splitting that gain across two amplifiers in series—each configured for a gain of ~31.6 (30 dB)—the bandwidth of each stage becomes roughly 316 kHz. You achieve the same total gain of 1,000, but with 30 times the bandwidth. Furthermore, cascading prevents the massive feedback resistor ratios required in single-stage designs, which introduce stray capacitance and high-frequency oscillation.
Component Behavior and Design Walkthrough
Let us design a practical two-stage non-inverting cascade using a single dual-op-amp IC, the NE5532. This chip is ideal because it packages two independent, low-noise amplifiers in a single 8-pin DIP, minimizing parasitic trace inductance between Node B and Stage 2.
Stage 1: Low-Noise Input (Gain = 10)
The first stage dictates the noise floor of the entire system (per Friis' formula for noise). We keep the gain moderate but high enough to elevate the signal above the thermal noise of the second stage.
- Feedback Resistor (Rf1): 90 kΩ (1% metal film)
- Ground Resistor (Rg1): 10 kΩ (1% metal film)
- Gain: $1 + (90k / 10k) = 10$
Stage 2: High-Swing Output (Gain = 10)
The second stage takes the 10x amplified signal and pushes it to the final voltage swing.
- Feedback Resistor (Rf2): 90 kΩ (1% metal film)
- Ground Resistor (Rg2): 10 kΩ (1% metal film)
- Gain: $1 + (90k / 10k) = 10$
Total System Gain: $10 \times 10 = 100$ (40 dB).
Behavior Matrix: What Changes When Components Shift?
| Component Altered | Modification | Effect on Stage 1 (Node B) | Effect on Total Output (Node C) |
|---|---|---|---|
| Rf1 (Feedback) | Shorted | Gain drops to 1 (Unity buffer) | Total gain drops to 10; system noise floor dominates the weak signal |
| Rg1 (Ground Ref) | Open Circuit | Output saturates to +13V (Positive rail) | Stage 2 amplifies the DC offset; Vout hard-rails to maximum positive voltage |
| Rg2 (Ground Ref) | Increased to 100kΩ | No change (Stage 1 operates normally) | Stage 2 gain drops to 1.9; Total system gain drops to 19 |
| Power Bypass Caps | Removed | High-frequency parasitic oscillation begins | Vout shows 1MHz+ ringing, clipping the intended audio/sensor signal |
Extreme Failure Modes: Open and Short Circuits
When debugging cascaded amplifiers on the bench, understanding how the topology fails at the extremes saves hours of oscilloscope probing. Unlike parallel circuits where a short might just blow a fuse, series signal chains propagate DC errors catastrophically.
Scenario A: Shorted Coupling Capacitor (AC-Coupled Designs)
If you insert a DC-blocking capacitor between Node B and Stage 2, and that capacitor fails short, the DC bias voltage of Stage 1 (usually half-rail in single-supply designs, or 0V in split-supply) is fed directly into Stage 2. Stage 2 amplifies this DC offset by its gain factor, instantly slamming Node C into the power rail. The amplifier will not pass AC signals until the capacitor is replaced.
Scenario B: Open Feedback Loop (Rf1 or Rf2 Open)
If the feedback resistor physically breaks or loses contact on the breadboard, the op-amp operates in open-loop mode. With an open-loop gain of 100,000+, even microvolts of input offset voltage will cause the output to instantly latch to either the positive or negative supply rail. If this happens in Stage 1, Node B sits at ±13V, and Stage 2 will attempt to amplify that to ±130V, ultimately hard-railing at its own supply limits and potentially overheating the output transistors.
Step-by-Step Breadboard Testing
Never build both stages and apply power simultaneously. Debugging a cascaded circuit requires isolating Node B. Follow this exact sequence to verify the design.
- Power and Bypass: Insert the NE5532. Run red wire to Pin 8 (+15V) and black wire to Pin 4 (-15V). Place 100nF X7R ceramic capacitors physically adjacent to the IC, bridging Pin 8 to ground and Pin 4 to ground. Do not skip the bypass caps.
- Wire Stage 1 Feedback: Install Rf1 (90kΩ) between Pin 1 (Output) and Pin 2 (Inverting Input). Install Rg1 (10kΩ) between Pin 2 and ground.
- Inject and Verify Stage 1: Connect your function generator to Pin 3 (Non-inverting). Set it to 1 kHz, 50 mVpp sine wave. Probe Pin 1 with your oscilloscope. You must see exactly 500 mVpp. If you see a flat line or a square wave, check your ground connections on Rg1.
- Wire Stage 2 Interconnect: Run a short jumper from Pin 1 (Node B) to Pin 5 (Stage 2 Non-inverting Input).
- Wire Stage 2 Feedback: Install Rf2 (90kΩ) between Pin 7 and Pin 6. Install Rg2 (10kΩ) between Pin 6 and ground.
- Final System Verification: Probe Pin 7 (Node C). With the same 50 mVpp input, you should now read 5.0 Vpp. Check for high-frequency ringing on the oscilloscope; if present, add a small 100Ω isolation resistor in series with the output at Pin 7 to stabilize capacitive loads.
Frequently Asked Questions
Can I put power amplifiers in series to increase voltage swing?
In signal electronics, cascading op-amps is standard. However, putting power amplifiers (like audio Class-D or Class-AB output stages) in series to double the voltage swing across a load is highly complex. It requires floating power supplies for the upper amplifier and precise differential drive circuitry to ensure the common-mode voltage limits of the input stages are not exceeded. For most DIY and pro-audio applications, bridging two amplifiers in parallel (BTL - Bridge-Tied Load) to double the voltage swing across the load is vastly safer, cheaper, and more stable than stacking them in series.
Does putting amplifiers in series increase the noise floor?
Every active component adds thermal and shot noise. However, in a cascaded topology, the noise contribution of the second stage is divided by the gain of the first stage when referred back to the input. This is governed by Friis' formula for noise. Therefore, as long as your first stage (Node A to Node B) has sufficient gain (typically 10x to 20x) and uses low-noise components like the NE5532 or OPA2134, the noise added by the second stage is mathematically negligible. The critical rule is: never put a unity-gain buffer before a high-gain stage, or you will degrade the signal-to-noise ratio.
How do I prevent high-frequency oscillation when cascading high-gain amplifiers?
Oscillation in series amplifiers usually stems from parasitic capacitance coupling the output of Stage 2 back into the high-impedance input of Stage 1. To prevent this on a breadboard or PCB: 1. Keep the physical distance between Node C (Vout) and Node A (Vin) as large as possible. 2. Use a ground plane (or a continuous ground bus wire on a breadboard) to provide a low-impedance return path. 3. Insert a low-pass RC filter or a simple 100Ω ferrite bead between the power supply rails and the op-amp Vcc pins to decouple high-frequency supply bounce. For further reading on stability, refer to the operational amplifier basics and stability guides provided by standard electronics references.
