When a power supply fails on the bench, the blown MOSFET usually gets the blame. But look an inch away, and you will often find the actual victim: a capacitor baked beyond its thermal limits. Managing heat in high-current DC-DC converters, motor drives, and inverters requires understanding two distinct thermal behaviors. First, the capacitor temperature coefficient, which dictates how much capacitance shifts as the dielectric heats up. Second, the thermal resistance network (Rtheta) that determines how hot the component actually gets under load. If you ignore either, your circuit will drift out of regulation or suffer catastrophic dielectric breakdown.
Decoding the Capacitor Temperature Coefficient and Dielectric Classes
The term 'capacitor temperature coefficient' (TC) means something entirely different depending on the chemistry you are using. For multilayer ceramic capacitors (MLCCs), the TC defines the maximum allowable capacitance drift across a specific temperature range, governed by the EIA-198 standard. For aluminum electrolytics, the TC is less about capacitance drift and more about the exponential degradation of equivalent series resistance (ESR) and electrolyte evaporation rates at high temperatures.
When selecting ceramics for a timing circuit or a high-frequency snubber, you must match the EIA code to your expected board temperature. A Y5V capacitor might offer massive microfarad density in a tiny 0805 package, but its capacitance will crater by over 80% if the board reaches 85°C. Conversely, C0G (NP0) offers near-zero drift, making it mandatory for resonant LLC converters where timing precision dictates zero-voltage switching (ZVS).
| Dielectric / Type | EIA Code / Class | Temp Range (°C) | Capacitance Shift (TC Limit) | Primary Application |
|---|---|---|---|---|
| Ceramic (Class I) | C0G / NP0 | -55 to +125 | ±30 ppm/°C | Resonant tanks, RF, precision filters |
| Ceramic (Class II) | X7R | -55 to +125 | ±15% | Decoupling, general bypass, snubbers |
| Ceramic (Class II) | X5R | -55 to +85 | ±15% | Consumer electronics, low-cost bulk |
| Ceramic (Class III) | Y5V | -30 to +85 | +22% / -82% | Non-critical low-frequency coupling |
| Aluminum Electrolytic | Standard 85°C | -40 to +85 | ±20% (Initial), ESR doubles at limits | Low-cost bulk storage, audio crossovers |
| Aluminum Electrolytic | High-Temp 105°C | -40 to +105 | ±20% (Initial), extended life multiplier | Switch-mode power supplies, motor drives |
| Film (Metallized PP) | DC-Link / AC-Filter | -40 to +105 | ±2.5% to ±5% typical | High-ripple inverters, EV traction drives |
For a deeper dive into how DC bias and temperature interact to shrink MLCC capacitance, the TDK MLCC Technical Guide provides excellent characteristic curves showing the combined derating effects.
Thermal Path Math: From Junction to Ambient (and Core to Case)
To keep a capacitor within its rated temperature coefficient limits, you must manage the ambient temperature immediately surrounding it. This requires calculating the thermal path of the heat-generating semiconductors sharing the same PCB or enclosure. Let us run the math on a common scenario: an Infineon IRLZ44N MOSFET (TO-220 package) switching a 15A load, paired with a bulk DC-link capacitor.
The MOSFET is dissipating 12W of heat. The maximum allowed junction temperature ($T_J$) is 175°C, but for long-term reliability, we design for a target $T_J$ of 110°C in a 40°C ambient environment ($T_A$).
The fundamental thermal equation is:
T_J = T_A + P_D × (Rθ_JC + Rθ_CS + Rθ_SA)
- P_D (Power Dissipation) = 12W
- Rθ_JC (Junction-to-Case) = 1.5 °C/W (from IRLZ44N datasheet)
- Rθ_CS (Case-to-Sink) = 0.5 °C/W (using a Bergquist Sil-Pad 2000 thermal interface material)
Solving for the required heatsink thermal resistance ($Rθ_{SA}$):
110 = 40 + 12 × (1.5 + 0.5 + Rθ_SA)
70 = 12 × (2.0 + Rθ_SA)
5.83 = 2.0 + Rθ_SA
Rθ_SA = 3.83 °C/W
We need a heatsink with a thermal resistance of 3.83 °C/W or lower. A solid choice here is the Aavid Thermalloy 577102B04000G, an extruded aluminum TO-220 heatsink rated at roughly 2.6 °C/W in natural convection. This gives us a comfortable 1.2 °C/W margin. By keeping the MOSFET case cool, we prevent it from radiating IR heat and conducting PCB-trace heat into the neighboring electrolytic capacitor.
Datasheet $T_A$ assumes a perfectly ventilated environment. If your 12W MOSFET is inside a sealed IP65 plastic enclosure, the local ambient air temperature will rise until thermal equilibrium is reached. A 20°C internal rise means your capacitor is now baking in 60°C air, drastically altering its ripple current handling and accelerating electrolyte evaporation. Always calculate enclosure thermal resistance if the system is sealed.
Derating Curves, Airflow, and Enclosure Strategies
How hot is too hot? For a 105°C rated aluminum electrolytic capacitor, running at exactly 105°C at its maximum rated ripple current will yield its base life—typically 2,000 to 5,000 hours. That is barely eight months of continuous 24/7 operation. The industry rule of thumb, backed by Arrhenius kinetics, is that for every 10°C drop in core temperature, the capacitor's lifespan doubles. Dropping the core temp from 105°C to 85°C buys you 20,000 hours; dropping to 65°C yields 80,000 hours.
When interpreting a manufacturer's derating curve—such as those found in the Cornell Dubilier Aluminum Electrolytic Application Guide—look for the 'knee' in the ripple current multiplier graph. At 105°C, the multiplier is 1.0. At 85°C, you can safely push 1.3x the rated ripple current. At 65°C, you can push 1.7x. If your circuit demands high ripple, you must either oversize the capacitor or force the thermal path to drop the ambient temperature.
What airflow and enclosure changes buy you:
- Natural Convection to 1 m/s Forced Air: Adding a small 40mm fan pushing 1 meter per second of air across a cylindrical capacitor or extruded heatsink typically cuts the surface-to-ambient thermal resistance ($Rθ_{SA}$ or $Rθ_{CA}$) by 30% to 50%. This is the cheapest way to drop core temperatures by 15°C.
- Thermal Vias and Copper Pours: For surface-mount MLCCs and polymer capacitors, heat escapes primarily through the PCB pads. Stitching an array of 0.3mm thermal vias directly under the capacitor pads to an internal ground plane can reduce the thermal resistance to the board by up to 40%.
- Component Spacing: Never place an electrolytic capacitor directly downstream of a hot air path from a power resistor or MOSFET heatsink. A 10mm lateral offset can drop the local ambient by 10°C to 15°C.
Failure Signatures of Thermal Stress
When thermal management fails and the capacitor exceeds its temperature coefficient and absolute maximum ratings, the failure signatures are distinct based on the dielectric chemistry. Recognizing these on the bench tells you exactly where the thermal design went wrong.
1. Aluminum Electrolytic Venting and ESR Spikes
Excessive heat vaporizes the liquid electrolyte, increasing internal pressure until the mechanical vent (the scored cross on the can top) pops. Before it vents, you will see a massive spike in ESR and a drop in capacitance. On an oscilloscope, this manifests as increased high-frequency ripple voltage on the DC bus, often triggering false over-current faults in downstream switching regulators. If the vent is intact but the can is bulging, the capacitor experienced sustained operation 15°C to 20°C above its rated limit.
2. MLCC Micro-Cracking and Thermal Runaway
Ceramic capacitors do not 'dry out'; they crack. Rapid thermal cycling or excessive localized heat from wave soldering can cause micro-cracks in the barium titanate dielectric. These cracks allow moisture ingress, leading to a slow drop in insulation resistance. In high-voltage applications, this culminates in a short circuit. Furthermore, Class II ceramics (X7R, Y5V) exhibit a piezoelectric effect and significant capacitance loss under combined DC bias and high heat, potentially causing a control loop to cross into instability and oscillate, generating even more heat.
3. Film Capacitor Metallization Oxidation
Ultimately, treating the capacitor temperature coefficient as a static number on a datasheet is a recipe for field returns. By calculating the true thermal path, selecting appropriate heatsinks like the Aavid 577102B04000G, and leveraging forced airflow to exploit the 10°C life-doubling rule, you ensure the dielectric stays exactly where it belongs: in its optimal thermal sweet spot.
