The most practical application of a capacitor and resistor circuit on the modern workbench is the passive RC low-pass filter. When you need to convert a microcontroller's Pulse Width Modulation (PWM) output into a stable analog DC voltage, an RC filter is the default solution. It is cheap, requires no external power rails, and avoids the electromagnetic ringing inherent in inductor-based designs. The direct answer for 90% of hobbyist and prototyping PWM-to-DC applications is a series resistor followed by a shunt capacitor to ground, sized to place the cutoff frequency at roughly one-tenth of your PWM switching frequency.
The RC Low-Pass Topology: Nodes, Behavior, and Real Values
To design effectively, we must define the physical topology. A standard first-order RC low-pass filter consists of three primary nodes:
- Node A (Vin): The input signal (e.g., microcontroller GPIO pin).
- Node B (Vout): The junction between the resistor and capacitor. This is your filtered analog output.
- Node C (GND): The common ground reference.
The resistor is placed in series between Node A and Node B. The capacitor is placed in parallel (shunt) between Node B and Node C. The resistor limits the current charging the capacitor, while the capacitor stores charge and resists rapid voltage changes, effectively shorting high-frequency AC components to ground while passing the DC average.
Below is a data-dense reference table for standard E24/E6 component combinations. This allows you to quickly select real-world parts based on your target cutoff frequency ($f_c$).
| Target $f_c$ | Resistor (E24) | Capacitor (E6) | Actual $f_c$ | Time Constant ($\tau$) | Output Impedance |
|---|---|---|---|---|---|
| 10 Hz | 160 kΩ | 100 nF | 9.95 Hz | 16.0 ms | 160 kΩ |
| 100 Hz | 16 kΩ | 100 nF | 99.5 Hz | 1.60 ms | 16 kΩ |
| 1 kHz | 1.6 kΩ | 100 nF | 995 Hz | 160 µs | 1.6 kΩ |
| 10 kHz | 1.6 kΩ | 10 nF | 9.95 kHz | 16.0 µs | 1.6 kΩ |
Parameter Behavior Matrix
Understanding how the circuit reacts when you swap a single component is critical for tuning ripple versus response time.
| Component Change | Cutoff Frequency ($f_c$) | Time Constant ($\tau$) | Output Ripple | Step Response Time |
|---|---|---|---|---|
| Increase R | Decreases | Increases | Decreases | Slower |
| Decrease R | Increases | Decreases | Increases | Faster |
| Increase C | Decreases | Increases | Decreases | Slower |
| Decrease C | Increases | Decreases | Increases | Faster |
Failure Modes: What Breaks at the Extremes?
A capacitor and resistor circuit is robust, but component failures yield distinct, diagnosable symptoms. When troubleshooting a dead or noisy analog output, check these four extreme failure modes:
| Failure Mode | Electrical Result at Node B | Observable Symptom | Secondary Risk |
|---|---|---|---|
| R Opens | Node B floats (high impedance). | Output reads 0V or random noise; no response to PWM changes. | None, but downstream ADC may float and pick up EMI. |
| R Shorts | Node B connects directly to Node A. | Filter is bypassed. Output is full-amplitude PWM square wave. | Downstream components may be exposed to high-frequency switching noise. |
| C Opens | Node B passes AC and DC equally. | Filter is bypassed. Output is full-amplitude PWM square wave. | Same as R short; often caused by a cracked MLCC ceramic capacitor. |
| C Shorts | Node B is hard-tied to GND. | Output reads exactly 0.0V regardless of PWM duty cycle. | Resistor will dissipate $V^2/R$ watts. A 3.3V signal through a 100Ω R will burn a 1/4W resistor. |
Why Choose an RC Filter Over LC or Active Alternatives?
When designing a smoothing network, you have three main choices: passive RC, passive LC (inductor-capacitor), and active (op-amp based). For 95% of microcontroller DAC applications, the RC topology wins.
| Criteria | Passive RC Filter | Passive LC Filter | Active Op-Amp Filter |
|---|---|---|---|
| Bill of Materials (BOM) Cost | ~$0.02 (1x R, 1x C) | ~$0.80+ (Inductors are expensive) | ~$1.50+ (Op-amp, R, C, decoupling) |
| Board Space | Minimal (0603 or 0805 SMD) | Large (Inductors require 3D volume) | Moderate (SOIC-8 + passives) |
| EMI / Ringing | None (Overdamped by default) | High risk of resonance ringing | Low, but op-amp can oscillate if unstable |
| Power Requirements | None (Passive) | None (Passive) | Requires VCC and VEE (or rail-to-rail) |
| Output Drive Capability | Poor (Limited by R value) | Good (Low DC resistance) | Excellent (Op-amp output stage) |
The Verdict: Choose the RC filter when your load is high-impedance (like an ADC input or an oscilloscope probe) and BOM cost/space is critical. Choose an LC filter only when driving low-impedance power loads (like a motor or LED string) where the series resistance of an RC filter would cause unacceptable voltage drop and heat. Choose an active filter when you need to drive a heavy load while maintaining a sharp cutoff slope (All About Circuits).
Design Walkthrough: Smoothing a 5kHz ESP32 PWM Signal
Let's design a real circuit. We are using an ESP32's LEDC peripheral to generate a 5kHz PWM signal at 3.3V logic levels, and we need a clean DC voltage to feed into an external analog sensor reference pin. Our target ripple is less than 20mV peak-to-peak.
Step 1: Determine the Target Cutoff Frequency
A standard rule of thumb for acceptable PWM smoothing is to set the RC cutoff frequency ($f_c$) to one-tenth of the PWM frequency.
$f_{PWM} = 5000 \text{ Hz}$
$f_c = 500 \text{ Hz}$
Step 2: Select the Capacitor
We start by picking the capacitor because standard capacitor values (E6 series) are fewer than resistor values. We need a value large enough to smooth the ripple, but small enough to avoid slow step-response times. A 100 nF (0.1 µF) X7R ceramic capacitor in an 0805 package (e.g., Murata GRM21BR71H104KA88) is a bench staple. X7R dielectric is chosen over Y5V because X7R maintains its capacitance value under DC bias, whereas Y5V can lose up to 50% of its rated capacitance at 3.3V.
Step 3: Calculate the Resistor
Using the standard cutoff frequency formula $f_c = \frac{1}{2 \pi R C}$, we solve for R:
$R = \frac{1}{2 \pi \times 500 \times 100 \times 10^{-9}}$
$R \approx 3183 \text{ \Omega}$
The nearest standard 1% E96 resistor value is 3.16 kΩ, but the more common E24 value is 3.3 kΩ. Let's use 3.3 kΩ (e.g., Vishay CRCW06033K30FKEA).
Step 4: Verify the Actual Performance
With R = 3.3 kΩ and C = 100 nF:
Actual $f_c = \frac{1}{2 \pi \times 3300 \times 100 \times 10^{-9}} = 482 \text{ Hz}$
Time Constant ($\tau$) = $R \times C = 330 \text{ \mu s}$.
At a 50% duty cycle, the output DC voltage will be 1.65V. The peak-to-peak ripple voltage ($V_{ripple}$) can be approximated by $V_{ripple} \approx \frac{V_{peak}}{4 \times f_{PWM} \times R \times C}$.
$V_{ripple} \approx \frac{3.3}{4 \times 5000 \times 0.00033} \approx 5 \text{ mV}$.
This easily meets our <20mV requirement. For deeper mathematical modeling of passive networks, refer to the Electronics Tutorials low-pass filter guide.
Step-by-Step Breadboard Testing and Verification
Theory only gets you so far; parasitic capacitance and breadboard contact resistance alter real-world behavior. Here is how to verify your capacitor and resistor circuit on the bench using the Espressif LEDC API to drive the PWM.
- Wire the Topology: Insert the 3.3 kΩ resistor into the breadboard. Connect one leg to your ESP32 GPIO pin (Node A). Connect the other leg to an empty row (Node B). Insert the 100 nF capacitor with one leg in the same row as Node B, and the other leg to the ground rail (Node C). Connect the ESP32 GND to the same ground rail.
- Configure the Oscilloscope: Connect the scope probe tip to Node B and the ground clip to Node C. Set the probe attenuation to 1X (or 10X and adjust scope settings accordingly). Set the timebase to 500 µs/div and the voltage scale to 1V/div.
- Set the Trigger: Trigger on the rising edge of the PWM signal at Node A (use a second channel if available) to stabilize the display. Alternatively, trigger on Node B's DC average.
- Program the Microcontroller: Flash a simple script to the ESP32 configuring the LEDC timer for 5kHz and set the duty cycle to 50% (4096 on a 13-bit resolution scale).
- Measure the DC Average: Switch the oscilloscope channel coupling to DC. Use the scope's built-in measurement tools to read the 'Mean' or 'Average' voltage. It should read 1.65V (±50mV due to component tolerance).
- Measure the AC Ripple: Switch the channel coupling to AC. This blocks the 1.65V DC offset and amplifies the ripple. Adjust the voltage scale to 10mV/div. Measure the peak-to-peak (Vpp) voltage. You should see a sawtooth-like wave measuring approximately 5mV to 10mV Vpp.
- Test the Step Response: Change the PWM duty cycle from 0% to 100% in code. Observe Node B on the scope in DC coupling. You should see an exponential curve rising to 3.3V. Measure the time it takes to reach 63.2% of 3.3V (2.08V). This measured time is your empirical Time Constant ($\tau$), which should be very close to the calculated 330 µs.
By following this topology and verification process, you eliminate the guesswork from analog signal conditioning. The capacitor and resistor circuit remains the most reliable, cost-effective method for bridging the digital-to-analog gap on the workbench.
