When you wire a capacitor in series, you are making a deliberate trade-off: you sacrifice total capacitance to increase the network's overall voltage rating, or to create a precise capacitive voltage divider for AC signals. In modern 800V DC architectures—common in 2026 SiC-based EV chargers and solar string inverters—finding a single film capacitor with the required microfarad rating and a 1000V+ breakdown voltage often means paying a massive premium for a physically enormous component. Stacking lower-voltage capacitors in series solves the availability and size problem, but it introduces a hidden lethal flaw if you ignore leakage current mismatch.
The Core Topology: Nodes, Math, and the Parallel Alternative
Consider a basic two-capacitor series network. The topology consists of three distinct nodes:
- Node A (HV Input): The high-voltage DC bus connection.
- Node B (Midpoint): The junction between the two capacitors.
- Node C (Ground/Return): The low-side reference.
The equivalent capacitance ($C_{eq}$) drops according to the reciprocal formula: $1/C_{eq} = 1/C_1 + 1/C_2$. If $C_1 = C_2$, the total capacitance is exactly half of a single unit. Meanwhile, the theoretical voltage rating adds linearly ($V_{max} = V_{C1} + V_{C2}$).
Why this topology over parallel? Wiring capacitors in parallel increases total capacitance while maintaining the voltage rating of the lowest-rated component in the bank. You use parallel when you need to store more energy or lower the equivalent series resistance (ESR) at a fixed voltage. You use series strictly when your bus voltage exceeds the maximum rated voltage of readily available, cost-effective capacitors, or when you need Node B to act as an AC-coupled midpoint reference.
Behavior Matrix and Failure Mode Contrast
Understanding how the network reacts to component drift or catastrophic failure is critical for high-voltage safety. Here is the behavior matrix for a two-capacitor series string:
| Event / Condition | Effect on $C_{eq}$ | Effect on Node B Voltage | Physical Consequence |
|---|---|---|---|
| $C_1$ increases (tolerance drift) | Increases slightly | Drops (Node B moves closer to GND) | $C_2$ sees higher voltage stress. |
| $C_1$ leakage increases | No change in nominal $C_{eq}$ | Rises (Node B moves toward HV) | $C_2$ overvoltages without balancing resistors. |
| Extreme: $C_1$ shorts internally | $C_{eq}$ becomes $C_2$ | Node B = Node A (Full HV bus) | $C_2$ takes 100% of bus voltage. If $V_{bus} > V_{C2\_rating}$, $C_2$ vents or explodes in a cascade failure. |
| Extreme: $C_1$ opens internally | $C_{eq}$ drops to ~0 (stray only) | Node B floats unpredictably | Snubber/divider function fails. Node B may arc to nearby traces via stray capacitance. |
The cascade failure mode (a short in one element destroying the remaining elements) is the primary reason series capacitor banks require careful derating and physical spacing on a PCB to prevent shrapnel damage to surrounding logic circuits.
Design Walkthrough: 800V DC Bus Snubber Network
Let’s design a snubber network for an 800V nominal DC bus (typical for a 2026 SiC MOSFET inverter). We need approximately 0.22µF of capacitance to dampen high-frequency ringing. A single 1000V, 0.22µF polypropylene film capacitor (like the Cornell Dubilier 940C series) is physically massive and costs upwards of $18 per unit in low volumes.
The Series Solution: We will use two WIMA MKP10 0.47µF, 630VDC film capacitors in series.
1. Calculate Equivalent Capacitance and Voltage
- $C_{eq} = (0.47 \times 0.47) / (0.47 + 0.47) = 0.235\mu F$ (Acceptable tolerance for a snubber).
- Theoretical Voltage Rating = $630V + 630V = 1260V$. Derated by 20% for high-altitude/transient safety, we have a comfortable 1000V working limit for an 800V nominal bus.
2. Size the Balancing Resistors
To force equal voltage division, the current flowing through our external balancing resistors must be at least 10 times the maximum expected leakage current of the capacitors. Film capacitors have excellent leakage, typically modeled by an RC time constant ($\tau$) of $>100,000$ seconds. However, a practical rule of thumb for high-voltage film caps is to target a balancing current of 1mA to 2mA.
- Target voltage per cap = 400V (half of 800V).
- Target current = 1.8mA.
- $R_{bal} = 400V / 0.0018A \approx 220,000\Omega$ (220kΩ).
3. Calculate Resistor Power Dissipation
This is where many hobbyist designs fail. The resistors will constantly dissipate heat.
- $P = V^2 / R = 400^2 / 220,000 = 0.72W$ per resistor.
- Component Pick: Do not use standard 0.25W through-hole resistors. Select Vishay PR02 1W metal film resistors (or 2W for extra thermal margin). Place them physically adjacent to the capacitors on the PCB to ensure the balancing network survives if a capacitor lead fractures.
Step-by-Step Breadboard Testing & Verification
Follow these numbered steps to verify your series design on the bench:
- Assemble the Low-Voltage Equivalent: Insert the two 0.47µF capacitors into a breadboard. Wire them in series. Connect the two 220kΩ balancing resistors in parallel with each respective capacitor.
- Apply Safe DC: Connect a bench power supply set to 48V DC across Node A and Node C. (48V is well below the 630V rating and safe for breadboard probing).
- Verify the Midpoint: Using a calibrated multimeter, measure the DC voltage at Node B relative to Node C. It should read exactly 24.0V (±0.5V). This proves the 220kΩ resistors are successfully swamping any minor leakage mismatches between the two capacitors.
- Simulate a Balancing Failure: Power down the supply, remove one of the 220kΩ resistors, and re-apply power. Watch the multimeter at Node B. Over the next 30 to 60 seconds, you will see the voltage drift away from 24V (often climbing to 28V or dropping to 18V) as the intrinsic leakage mismatch of the two capacitors takes over. This visually proves why the resistors are non-negotiable in high-voltage applications.
- Measure AC Impedance (Optional): If this is for an AC snubber, inject a 100kHz square wave via a function generator and a small series resistor, and probe Node B with an oscilloscope to verify the capacitive divider ratio holds at high frequencies without excessive ringing.
Decision Tree: Series, Parallel, or Single High-Voltage?
Use this decision path to finalize your bill of materials. Do not default to a series network out of habit; use it only when the physics or economics demand it.
| Design Constraint | Topology Choice | Concrete Component Recommendation |
|---|---|---|
| Need high capacitance, bus voltage is below standard cap ratings (e.g., 400V bus, need 10µF). | Parallel | Multiple standard 450V electrolytic or film caps in parallel to lower ESR and share ripple current. |
| Need low capacitance, bus voltage exceeds standard ratings, but physical PCB space is abundant and budget is high. | Single HV Cap | Cornell Dubilier 940C or Kemet C4AE series single high-voltage film capacitor. No balancing resistors needed. |
| Need low capacitance, bus voltage exceeds standard ratings, and PCB space / BOM cost is strictly limited. | Series | WIMA MKP10 or Panasonic EZP-E series stacked in series, mandatory 1W+ metal film balancing resistors. |
| Need high capacitance AND extreme voltage (e.g., 100µF at 2000V for a pulse forming network). | Series-Parallel Matrix | Requires custom busbars, individual fuse protection per series string, and active voltage monitoring. Defer to specialized HV engineering. |
The Default Recommendation: Always attempt to source a single capacitor with the correct voltage and capacitance rating first (such as the Kemet C4AE series). A single component eliminates the risk of cascade failures, removes the continuous power loss of balancing resistors, and simplifies PCB layout. Only commit to a capacitor in series network when the single-component solution exceeds your BOM cost by more than 30% or physically cannot fit inside your enclosure constraints. When you do build the series string, never skip the balancing resistors, and always calculate their steady-state power dissipation.
