When evaluating the capacitor function in circuit design, hobbyists often default to using capacitors solely for bulk power decoupling. But when you interface analog sensors with a microcontroller like the ESP32, the capacitor takes on a much more critical role: signal conditioning and charge reservoir stabilization. The ESP32’s internal analog-to-digital converter (ADC) uses a successive approximation register (SAR) architecture, which switches an internal sampling capacitor (typically 10pF to 20pF) onto the input pin during conversion. Without an external capacitor to supply this instantaneous charge, your readings will suffer from severe kickback noise and ghost voltages.
This guide walks through the design, component selection, and verification of a passive RC low-pass filter topology to solve this exact problem, terminating in a concrete bill of materials you can order today.
The Core Topology: RC Low-Pass Filter Node Map
The most reliable way to condition a DC or slow-moving analog signal (like a thermistor or light dependent resistor) before it hits a microcontroller ADC is a first-order passive RC low-pass filter. This topology serves two distinct capacitor functions in the circuit simultaneously: it attenuates high-frequency electromagnetic interference (EMI), and it acts as a local charge reservoir to satisfy the ADC’s internal sampling switch.
- Node A ($V_{in}$): The raw analog signal source (e.g., the wiper of a potentiometer or a sensor voltage divider).
- Node B ($V_{out}$): The junction between the series resistor and the shunt capacitor. This node connects directly to the microcontroller ADC pin (e.g., ESP32 GPIO 34).
- Node C ($GND$): The common ground reference, shared by the sensor, the capacitor, and the microcontroller.
The resistor ($R$) is placed in series between Node A and Node B. The capacitor ($C$) is placed in parallel with the ADC input, bridging Node B and Node C. The cutoff frequency ($f_c$) is determined by the standard formula: $f_c = \frac{1}{2 \pi R C}$.
Component Behavior and Failure Extremes
Understanding how this topology reacts to component drift or catastrophic failure is what separates a bench prototype from a field-deployable device. Below is the behavior matrix detailing what happens when we alter the elements, followed by the hard failure modes.
Parameter Behavior Table
| Element Changed | Direction | Effect on Cutoff Freq ($f_c$) | Effect on ADC Settling Time | Effect on Source Loading |
|---|---|---|---|---|
| Resistor ($R$) | Increase | Decreases (Better noise rejection) | Increases (Slower response) | Decreases (Less draw from sensor) |
| Resistor ($R$) | Decrease | Increases (Worse noise rejection) | Decreases (Faster response) | Increases (May sag sensor voltage) |
| Capacitor ($C$) | Increase | Decreases (Better noise rejection) | Increases (Slower response) | No direct effect on DC load |
| Capacitor ($C$) | Decrease | Increases (Worse noise rejection) | Decreases (Faster response) | Risk of ADC charge kickback errors |
Extreme Failure Modes (Open vs. Short)
When troubleshooting a board that returns erratic ADC values, use this decision path to isolate the fault:
- Capacitor Shorts: Node B is pulled directly to Node C (GND). The ADC will read a hard 0V. The sensor output may overheat if it lacks current limiting.
- Capacitor Opens: The filter is defeated. High-frequency noise passes unattenuated to Node B. More critically, the ADC’s internal sampling capacitor has no external reservoir, resulting in non-linear, noisy readings that fluctuate with the MCU's internal clock switching.
- Resistor Shorts: Node A connects directly to Node B. The filter is defeated (identical symptoms to an open capacitor), and the sensor now directly drives the ADC’s switched-capacitor load, potentially causing signal droop.
- Resistor Opens: Node B becomes high-impedance (floating). The ADC pin will pick up ambient 50/60Hz mains hum and digital switching noise, resulting in random, ghost voltages across the full 0-3.3V scale.
Design Walkthrough: Sizing for an ESP32 ADC
Let’s design a filter for a 10k NTC thermistor voltage divider reading ambient temperature. Temperature changes slowly, so we can afford a low cutoff frequency to aggressively strip out 50/60Hz mains hum and RF interference. We will target a cutoff frequency ($f_c$) of roughly 100Hz.
Step 1: Establish the Charge Reservoir Rule
To prevent ADC kickback errors, the external capacitor must be at least 100 times larger than the ADC’s internal sampling capacitor. The ESP32 ADC input capacitance is approximately 12pF. Therefore, our minimum $C$ is $12pF \times 100 = 1.2nF$. We will go much larger to ensure a stable voltage during the sampling window.
Step 2: Pick the Capacitor ($C$)
We select a standard E6 value of 100nF (0.1µF). This provides a massive 8,300x charge reservoir ratio, virtually eliminating sampling kickback.
Step 3: Calculate the Resistor ($R$)
Rearranging the cutoff formula: $R = \frac{1}{2 \pi f_c C}$
$R = \frac{1}{2 \pi \times 100Hz \times 100 \times 10^{-9}F} \approx 15,915\Omega$
Step 4: Select the Real Component
The closest standard E24 resistor value is 15kΩ.
Recalculating the actual cutoff: $f_c = \frac{1}{2 \pi \times 15000 \times 100 \times 10^{-9}} = 106.1Hz$. This is perfect for a slow-moving thermal sensor.
- Resistor: Yageo RC0603FR-0715KL (15kΩ, 1%, 0603 SMD) or standard 1/4W 15k through-hole.
- Capacitor: See dielectric decision tree below for the exact part number.
Dielectric Decision Tree: X7R vs. C0G/NP0
Not all 100nF capacitors behave the same way. The dielectric material dictates how the capacitance shifts under applied DC voltage and temperature changes. If you pick the wrong dielectric, your 100Hz filter might drift to 140Hz on a hot day, or introduce microphonic noise.
| Criteria | X7R (General Purpose) | C0G / NP0 (Precision) |
|---|---|---|
| DC Bias Effect | Loses up to 40% capacitance at rated voltage | 0% change (Highly stable) |
| Temperature Coefficient | ±15% over -55°C to +125°C | ±30ppm/°C (Virtually flat) |
| Piezoelectric Noise | High (generates voltage when vibrated) | None |
| Cost (0603 100nF) | ~$0.01 | ~$0.05 |
The Decision Path
- IF the signal is an audio AC coupling or general power rail bypass → Choose X7R.
- IF the required capacitance is >1µF and physical size is constrained → Choose X5R or X7R (C0G is rarely available above 100nF in small footprints).
- IF the signal is a precision DC measurement (like our thermistor ADC) where DC bias derating and microphonic noise will corrupt the reading → Choose C0G/NP0.
The Concrete Pick: For this ESP32 ADC filter, we terminate the decision tree at the Murata GRM1885C1H104JA01. It is a 100nF, 50V, C0G/NP0 dielectric capacitor in an 0603 package. It guarantees the capacitance will not drop under the 3.3V DC bias of the ESP32, ensuring our 106Hz cutoff remains mathematically exact regardless of board temperature.
Step-by-Step Breadboard Verification
Before committing this topology to a printed circuit board, verify the attenuation and settling time on a breadboard. You will need a function generator, a digital multimeter (DMM), and ideally an oscilloscope.
- Wire the Topology: Insert the 15kΩ resistor into the breadboard. Connect one leg to your signal source rail (Node A). Connect the other leg to an empty row (Node B). Insert the 100nF C0G capacitor bridging Node B and the ground rail (Node C).
- Establish the Baseline: Set your function generator to output a 100Hz sine wave at 1.0V peak-to-peak (Vpp). Connect the generator output to Node A. Probe Node A with your scope to verify the clean 1.0Vpp input.
- Measure the Cutoff Attenuation: Move the scope probe to Node B. Because 100Hz is near our 106Hz cutoff frequency ($f_c$), the signal should be attenuated by approximately -3dB. Your scope should read roughly 0.707Vpp. If it reads 1.0Vpp, your capacitor is open or missing.
- Verify High-Frequency Rejection: Change the function generator to 10kHz (well past the cutoff). The amplitude at Node B should drop by roughly -40dB (a factor of 100), reading around 10mVpp on the scope. This confirms the capacitor is effectively shunting high-frequency noise to ground.
- Test ADC Settling (The Step Response): Switch the generator to a 10Hz square wave (0V to 3.3V). Probe Node B. You should see an exponential RC charging curve. Measure the time it takes to reach 63.2% of the final voltage (one time constant, $\tau = R \times C$). With 15kΩ and 100nF, $\tau$ should be exactly 1.5 milliseconds. If the curve is a sharp vertical line, your resistor is shorted.
Why Passive RC Beats Active Filtering Here
A common alternative to the passive RC filter is an active Sallen-Key topology or a simple op-amp voltage follower (buffer) placed before the ADC. While an active filter provides a sharper roll-off and isolates the sensor from the ADC’s input impedance entirely, it is the wrong choice for this specific application for three reasons:
- Quiescent Current: A rail-to-rail op-amp like the MCP6001 draws roughly 100µA of quiescent current. In a battery-powered ESP32 deep-sleep sensor node, that continuous draw dwarfs the MCU's sleep current. The passive RC draws exactly 0mA quiescent.
- Noise Injection: Every active component introduces its own input voltage noise and thermal noise. For a 12-bit SAR ADC reading a slow DC signal, the inherent noise floor of a cheap op-amp will degrade your effective number of bits (ENOB) more than the passive filter's gentle -20dB/decade roll-off.
- Cost and Board Space: The passive RC requires two components costing less than $0.06 total and occupies a fraction of a square millimeter in SMD. An active solution requires the op-amp IC, dual power rail decoupling capacitors, and feedback resistors, ballooning the BOM cost past $0.80 and consuming valuable PCB real estate.
By understanding the true capacitor function in circuit design—specifically its dual role as a frequency-dependent shunt and a transient charge reservoir—you can confidently deploy the Murata C0G 100nF and 15kΩ resistor pair to achieve clean, stable ADC readings without the overhead of active silicon.
