Topology and the "Inverted" Scaling Rule
The standard capacitive voltage divider consists of two capacitors in series. To analyze the circuit, we define three specific nodes:
- Node A (Input): The AC signal source connection.
- Node B (Output/Midpoint): The junction between the two capacitors where the divided voltage is measured.
- Node C (Ground): The common reference point connected to the bottom of the second capacitor and the signal source return.
Capacitor C1 is placed between Node A and Node B. Capacitor C2 is placed between Node B and Node C. The capacitive reactance (X_C) of each component is defined as X_C = 1 / (2πfC). Because reactance is inversely proportional to capacitance, a larger capacitor presents a smaller impedance to AC current. Therefore, the larger capacitor drops less voltage. This is the exact inverse of a resistive divider, where a larger resistor drops more voltage. If C1 is 10nF and C2 is 90nF, C1 has nine times the reactance of C2, meaning it will drop 90% of the input voltage, leaving 10% at Node B.
Behavior Matrix and Failure Extremes
When designing protection or sensing circuits, you must know exactly how the midpoint voltage (Node B) reacts to component drift, aging, or catastrophic failure. The table below maps the behavior of the divider across nominal, degraded, and extreme fault conditions.
| Condition | C1 Status (Top) | C2 Status (Bottom) | V_out (Node B) Result | Physical Reason / Hazard |
|---|---|---|---|---|
| Nominal (10:1 Ratio) | 10nF | 90nF | 10% of V_in | Designed reactance ratio maintained. |
| C1 Drifts High (+20%) | 12nF | 90nF | 11.7% of V_in | Lower X_C1 shifts more voltage to C2. Output rises. |
| C2 Drifts Low (-20%) | 10nF | 72nF | 12.1% of V_in | Higher X_C2 forces it to absorb more voltage. Output rises. |
| C1 Fails Short | 0Ω (Short) | 90nF | 100% of V_in | Critical Fault: Full input voltage hits Node B. Destroys downstream ADCs or logic. |
| C1 Fails Open | ∞Ω (Open) | 90nF | 0V (Floating) | AC path broken. Node B floats to ground via parasitic leakage or downstream pull-downs. |
| C2 Fails Short | 10nF | 0Ω (Short) | 0V | Node B is hard-shorted to ground. C1 limits current, preventing a source fault, but signal is lost. |
| C2 Fails Open | 10nF | ∞Ω (Open) | ~100% of V_in | Critical Fault: Node B couples directly to V_in through C1, limited only by high-impedance scope/probe loads. |
Capacitive vs. Resistive Dividers: Choosing the Topology
Why use a capacitor divider instead of simply dropping the voltage with resistors? The decision hinges on power dissipation, frequency response, and DC isolation.
| Criteria | Resistive Divider | Capacitive Divider |
|---|---|---|
| Real Power Dissipation | High (I²R losses generate heat) | Near Zero (Ideally lossless, only ESR causes minor heating) |
| DC Response | Passes DC and AC equally | Blocks DC entirely (Infinite reactance at 0Hz) |
| High-Frequency Limits | Limited by parasitic parallel capacitance (acts as a low-pass filter) | Limited by Equivalent Series Inductance (ESL) and skin effect |
| Best Application | DC bias networks, low-frequency analog scaling, feedback loops | High-voltage AC sensing, RF impedance matching, AC coupling |
For a 120VAC mains monitoring circuit, a 1MΩ / 10kΩ resistive divider continuously dissipates roughly 14 milliwatts. While small, in a sealed, high-density smart meter enclosure, that heat compounds. A capacitive divider using 100nF and 1nF capacitors dissipates virtually zero real power, making it the superior choice for high-efficiency AC scaling.
Design Walkthrough: 10:1 Scaling for a 100kHz Signal
Let’s design a divider to scale a 20V_pp, 100kHz AC signal down to 2V_pp for an oscilloscope or high-speed ADC input. We need a 10:1 ratio, meaning C1 / (C1 + C2) = 0.1.
We will select C1 = 10nF and C2 = 90nF. The total series capacitance is 9nF. At 100kHz, the total reactance is roughly 176Ω, drawing about 113mA of AC current from the source—well within the limits of most bench function generators.
The Dielectric Trap: The most common mistake hobbyists make here is grabbing standard X7R or Y5V multilayer ceramic capacitors (MLCCs) from their kit. X7R is a Class II dielectric with a severe voltage coefficient; as the AC voltage swings, the capacitance value dynamically changes, introducing massive harmonic distortion into your scaled signal. Furthermore, Class II ceramics exhibit piezoelectric noise (microphonics). For signal-path AC dividers, you must use Class I dielectrics like C0G (also known as NP0), which maintain stable capacitance regardless of voltage or temperature. Read more on MLCC voltage coefficients to understand why dielectric selection dictates signal integrity.
| Component | Value | Real-World MPN (Example) | Dielectric | Voltage Rating | ESR (Approx) |
|---|---|---|---|---|---|
| C1 (Top) | 10nF | Kemet C0805C103J1GACTU | C0G / NP0 | 100V | < 50mΩ |
| C2 (Bottom) | 90nF | Wurth 885012207082 (Parallel 9x 10nF) | C0G / NP0 | 50V | < 10mΩ (Effective) |
| Bleeder Resistor | 1MΩ | Vishay CRCW08051M00FKEA | N/A (Thick Film) | 150V | N/A |
Step-by-Step Breadboard Verification
Testing a high-frequency capacitive divider on a breadboard introduces parasitic variables that can skew your results. Follow this exact sequence to verify your design.
- Prep the Board and Components: Insert C1 and C2 in series across the breadboard's power rails. Keep the physical distance between Node A, Node B, and Node C as short as possible to minimize stray parallel capacitance (which typically adds 2pF to 5pF per row on a standard breadboard).
- Install the Bleeder Resistor: Place the 1MΩ resistor in parallel with C2. This provides a DC path to ground, preventing static charge buildup at Node B which could otherwise damage your oscilloscope's input stage.
- Configure the Signal Generator: Set your function generator to output a 100kHz sine wave, 20V_pp amplitude, with a 0V DC offset. Connect the BNC-to-alligator leads to Node A (signal) and Node C (ground).
- Compensate the Oscilloscope Probe: Before probing Node B, attach your 10x oscilloscope probe to the scope's calibration square-wave output and adjust the probe's trimmer capacitor until the square wave edges are perfectly flat. An uncompensated probe will act as an unintended parallel capacitor, destroying your high-frequency divider ratio. For a deeper understanding of probe loading, review oscilloscope probe fundamentals.
- Measure and Calculate: Attach the 10x probe to Node B. Measure the peak-to-peak voltage. You should see approximately 2.0V_pp. If you see 1.6V_pp or lower, the parasitic capacitance of your breadboard and probe (typically 12pF to 15pF in parallel with C2) is altering the ratio.
- Verify Phase Shift: Trigger the scope on Channel 1 (Node A) and view Channel 2 (Node B). In a purely capacitive divider, the voltage at Node B should be exactly in phase with Node A. If you observe a phase shift, your capacitors have high Equivalent Series Resistance (ESR) or your signal generator's output impedance is interacting with the network.
By understanding the inverted scaling rule, selecting the correct Class I dielectrics, and accounting for probe parasitics, you can reliably use capacitor dividers for everything from ultrasonic sensor scaling to isolated mains monitoring.
