The charging equation of a capacitor is V(t) = Vs(1 - e-t/RC). This formula calculates the exact voltage across a capacitor at any given time t as it charges through a resistor from a DC voltage source. Whether you are designing a soft-start circuit for a power supply, sizing an RC delay for a microcontroller reset pin, or analyzing an analog filter, this exponential relationship is the foundational math governing the timing of your circuit.
The Core Charging Equation and Symbol Definitions
When a DC voltage is applied to a series resistor-capacitor (RC) network, the capacitor does not charge instantly. The resistor limits the initial inrush current, forcing the voltage across the capacitor to rise exponentially. The curve starts steep and gradually flattens out as it asymptotically approaches the source voltage.
The standard formula for the voltage across the capacitor at time t is:
V(t) = Vs × (1 - e-t / RC)
| Symbol | Parameter | Standard Unit | Description |
|---|---|---|---|
| V(t) | Voltage at time t | Volts (V) | The potential difference across the capacitor plates at a specific moment. |
| Vs | Source Voltage | Volts (V) | The constant DC supply voltage driving the circuit. |
| e | Euler's Number | Dimensionless | Mathematical constant approximately equal to 2.71828. |
| t | Time | Seconds (s) | The elapsed time since the charging voltage was applied. |
| R | Resistance | Ohms (Ω) | The series resistance limiting the charging current. |
| C | Capacitance | Farads (F) | The capacity of the component to store electrical charge. |
| τ (tau) | Time Constant | Seconds (s) | The product of R × C. Represents the time to reach ~63.2% of Vs. |
To ground this in reality, here is a data-dense reference table showing how standard bench components interact to create specific timing delays. Notice how the time to reach 99% charge (practically considered 'fully charged' in most digital logic applications) is always exactly 5τ.
| Application Scenario | Resistor (R) | Capacitor (C) | Time Constant (τ) | Time to 99% (5τ) |
|---|---|---|---|---|
| Microcontroller Reset Delay | 10 kΩ | 100 nF (0.1 μF) | 1.0 ms | 5.0 ms |
| Audio AC-Coupling Filter | 100 kΩ | 1 μF | 100 ms | 500 ms |
| Soft-Start Relay Delay | 47 kΩ | 220 μF | 10.34 s | 51.7 s |
| Supercapacitor RTC Backup | 100 Ω | 5.0 F | 500 s (8.3 min) | 2500 s (41.6 min) |
Assumptions, Limitations, and Unit Traps
When the Formula Applies (and Its Assumptions)
The charging equation of a capacitor is derived from Kirchhoff's Voltage Law (KVL) applied to a simple series RC loop. For the math to perfectly match reality, several assumptions must hold true:
- Constant DC Source: Vs must be a stiff, ideal voltage source. If your power supply sags under the initial inrush current (due to high internal impedance), the actual Vs in the equation will be lower at t=0 and recover over time, warping the curve.
- Linear, Constant Resistance: The resistor must be ohmic. If you use an NTC thermistor to limit inrush, R decreases as it heats up, breaking the constant-τ assumption.
- Zero Initial Charge: The standard formula assumes the capacitor starts at 0V. If it starts at an initial voltage (V0), the equation modifies to: V(t) = V0 + (Vs - V0)(1 - e-t/RC).
- Negligible Parasitics: It assumes ideal components. Real electrolytic capacitors have Equivalent Series Resistance (ESR) and leakage current. At high frequencies or with massive supercapacitors, parasitic inductance (ESL) and leakage will cause the measured bench voltage to deviate from the theoretical ideal.
Unit Mistakes That Break the Math
The most common reason hobbyists and engineering students get wildly incorrect answers is unit mismatch. The equation demands strict adherence to base SI units: Ohms, Farads, and Seconds.
Another frequent error is mixing time units. If your calculated τ is in seconds, your input for t must also be in seconds. Do not plug t in milliseconds while leaving RC in seconds.
Rearranged Forms for Circuit Design
On the workbench, you rarely know t and need to find V(t). Usually, you know your target voltage threshold and need to calculate the required resistor, capacitor, or delay time. According to foundational circuit theory documented by resources like Georgia State University's HyperPhysics, algebraic rearrangement of the natural logarithm yields the following design formulas:
| To Solve For: | Rearranged Equation | Design Use Case |
|---|---|---|
| Time (t) | t = -RC × ln(1 - (V(t) / Vs)) | Finding the exact delay before a logic pin crosses a threshold. |
| Resistance (R) | R = -t / [C × ln(1 - (V(t) / Vs))] | Sizing a current-limiting resistor for a specific charge time. |
| Capacitance (C) | C = -t / [R × ln(1 - (V(t) / Vs))] | Selecting a capacitor value to achieve a desired soft-start delay. |
| Source Voltage (Vs) | Vs = V(t) / (1 - e-t/RC) | Deducing the supply rail voltage from a known intermediate measurement. |
Note: 'ln' denotes the natural logarithm (base e), not the base-10 logarithm (log). Ensure your calculator is set to 'ln'.
Worked Examples with Unit Tracking
Let's apply the charging equation of a capacitor to two real-world bench scenarios, tracking every unit conversion and intermediate step.
Problem 1: Finding Voltage at a Specific Time
Scenario: You are building a delayed-enable circuit. You have a 12V DC source, a 4.7 kΩ carbon film resistor, and a 220 μF Panasonic FR-series electrolytic capacitor. What is the voltage across the capacitor exactly 0.5 seconds after power is applied?
Step 1: Convert to base SI units.
- Vs = 12 V
- R = 4.7 kΩ = 4,700 Ω
- C = 220 μF = 0.00022 F
- t = 0.5 s
Step 2: Calculate the Time Constant (τ).
- τ = R × C
- τ = 4,700 Ω × 0.00022 F = 1.034 seconds
Step 3: Apply the charging equation.
- V(0.5) = 12 × (1 - e-0.5 / 1.034)
- V(0.5) = 12 × (1 - e-0.48356)
- V(0.5) = 12 × (1 - 0.61658)
- V(0.5) = 12 × 0.38342
- V(0.5) = 4.60 Volts
At half a second, the capacitor has charged to roughly 38% of the source voltage, which makes sense because 0.5s is roughly half of one time constant (1.034s).
Problem 2: Finding Time to Reach a Logic Threshold
Scenario: You are designing a reset delay for an ESP32 microcontroller. The EN (enable) pin requires a logic HIGH of roughly 2.5V to boot. Your Vs is 3.3V. You have chosen a 100 kΩ resistor and a 10 μF ceramic capacitor. How long after power-on will the ESP32 boot?
Step 1: Convert to base SI units and identify variables.
- Vs = 3.3 V
- V(t) = 2.5 V (Target threshold)
- R = 100 kΩ = 100,000 Ω
- C = 10 μF = 0.00001 F
Step 2: Calculate τ and use the rearranged time formula.
- τ = 100,000 × 0.00001 = 1.0 second
- t = -RC × ln(1 - (V(t) / Vs))
- t = -1.0 × ln(1 - (2.5 / 3.3))
- t = -1.0 × ln(1 - 0.75757)
- t = -1.0 × ln(0.24242)
- t = -1.0 × (-1.417)
- t = 1.417 seconds
The ESP32 will remain in reset for approximately 1.42 seconds before the EN pin crosses the 2.5V threshold and the chip begins its boot sequence.
Realistic Magnitudes and Bench Verification
What Does a Realistic Answer Look Like?
Context is everything when evaluating your calculated results. If you are working with RF decoupling or high-speed digital logic, realistic time constants are in the nanosecond to microsecond range (using pF and nF capacitors). For analog audio filters and microcontroller delays, you will typically see millisecond to single-digit second magnitudes. If your calculation for a simple bench circuit yields a time constant of 4,000 seconds, you have almost certainly forgotten to convert microfarads to Farads.
Verifying on the Workbench
Theory assumes perfection; the bench reveals reality. To verify the charging equation of a capacitor physically, connect an oscilloscope (like a Rigol DS1054Z or Siglent SDS1104X-E) across the capacitor. Set the trigger to the rising edge of the DC source switching on, and use single-shot trigger mode.
When analyzing real-world electrolytic or supercapacitors, you will notice the curve never quite hits Vs. Instead, it asymptotes slightly below the source rail. This is due to leakage current. The capacitor acts as if it has a massive resistor in parallel with it, forming a voltage divider with your series charging resistor. Furthermore, high-ESR capacitors will show an immediate, tiny vertical voltage step at t=0 (equal to Iinrush × ESR) before the smooth exponential curve begins. Understanding these non-ideal behaviors is what separates textbook simulation from reliable, real-world hardware design. For deeper insights into non-ideal capacitor behaviors and derating, refer to application notes from manufacturers like All About Circuits and major component datasheets.
