A capacitive voltage divider steps down alternating current (AC) voltage using reactive impedance rather than resistive dissipation. For a 120VAC mains sensing application targeting a 3.3V microcontroller ADC, a capacitive divider dissipates less than 5 milliwatts of heat, whereas an equivalent resistive divider would waste over 1.5 watts and require bulky, expensive power resistors. This topology is the definitive choice for isolated or non-isolated low-power AC voltage monitoring, zero-crossing detection, and RMS measurement.
The Capacitive Voltage Divider Topology Explained
Unlike a resistive divider where voltage drops proportionally to resistance, a capacitive divider relies on capacitive reactance ($X_C = \frac{1}{2\pi f C}$). Because reactance is inversely proportional to capacitance, the voltage division formula is inverted compared to resistors: the smaller capacitor drops the larger share of the voltage.
The standard topology consists of four primary nodes:
- Node 1 ($V_{in}$): The AC source (e.g., 120VAC Hot line).
- Node 2 ($V_{mid}$): The junction between the series capacitor ($C_1$) and the shunt capacitor ($C_2$).
- Node 3 ($V_{out}$): The output measured across $C_2$, fed to the sensing circuitry.
- Node 0 (GND/Neutral): The AC return path and circuit common.
The ideal output voltage is calculated as:
$$V_{out} = V_{in} \times \frac{C_1}{C_1 + C_2}$$
Element Behavior Matrix
Understanding how component drift or tolerance affects the output is critical for precision sensing. Here is what happens when a single variable changes while others remain constant:
| Parameter Changed | Effect on $V_{out}$ | Effect on Phase Shift | Practical Consequence |
|---|---|---|---|
| Increase $C_1$ (Series) | Increases | Decreases slightly | Over-voltage risk to MCU ADC if tolerance is +20%. |
| Increase $C_2$ (Shunt) | Decreases | Decreases slightly | Signal drops below ADC noise floor; loss of resolution. |
| Increase Frequency ($f$) | No change (ideal) | No change | Impedance drops, increasing available current, but ratio holds. |
| Add Parallel Load ($R_L$) | Decreases heavily | Shifts toward 0° | Destroys the division ratio; capacitive dividers cannot supply high current. |
Why Capacitive Over Resistive? (The Decision Path)
Choosing between a capacitive divider, a resistive divider, or a transformer depends entirely on your load current and thermal constraints. A capacitive divider blocks DC and limits AC current without generating heat, but it cannot supply meaningful power to a load.
| Criterion | Resistive Divider | Capacitive Divider | Step-Down Transformer |
|---|---|---|---|
| Power Dissipation (120V to 3V) | High (>1W) | Negligible (<5mW) | Low (Core/Copper losses) |
| DC Compatibility | Yes | No (Blocks DC) | No (Blocks DC) |
| Current Delivery | Moderate | Microamps only | Amps |
| Galvanic Isolation | No | No | Yes |
| Board Footprint | Large (Power resistors) | Small (Film caps) | Massive |
- IF you need to measure DC voltage → Use a Resistive Divider.
- IF you need to power a load > 10mA from mains → Use a Transformer or isolated AC-DC switching supply.
- IF you need galvanic isolation for safety → Use a Transformer or isolated amplifier (e.g., AMC1301).
- IF you are measuring AC mains voltage (sensing only, < 1mA load) and want minimal heat/footprint → Use a Capacitive Voltage Divider.
Design Walkthrough: 120VAC to 3.3V ESP32 Sensing Circuit
Let's design a divider to step down 120VAC RMS (which is 169.7V Peak) to a safe peak voltage for an ESP32 ADC. The ESP32 ADC is notoriously non-linear above 3.1V, so we will target a maximum peak output of 2.5V, leaving safe headroom.
1. Calculate the Capacitance Ratio:
Target Ratio = $V_{out(peak)} / V_{in(peak)} = 2.5V / 169.7V = 0.01473$.
2. Select $C_2$ (Shunt Capacitor):
We need a stable, low-ESR film capacitor for the shunt. Let's select $C_2 = 1.0 \mu F$ (1000nF).
3. Calculate $C_1$ (Series Capacitor):
Using the formula $Ratio = C_1 / (C_1 + C_2)$:
$0.01473 = C_1 / (C_1 + 1000nF)$
$C_1 = 15nF$ (Standard E12 value).
4. Verify the Output:
$V_{out(peak)} = 169.7V \times (15 / 1015) = 2.50V$. Perfect.
5. Add Bleed and Safety Resistors:
Capacitors store lethal energy when unplugged. You must add bleed resistors.
• $R_{bleed1}$ (across $C_1$): 1M$\Omega$ (Discharges $C_1$ in < 0.1 seconds).
• $R_{bleed2}$ (across $C_2$): 100k$\Omega$ (Discharges $C_2$ in < 0.5 seconds).
• $R_{series}$ (between $V_{mid}$ and MCU pin): 1k$\Omega$ (Limits transient fault current into the MCU's internal ESD diodes).
Failure Modes: What Breaks at the Extremes?
A common mistake in capacitive divider designs is assuming the voltage ratio holds under fault conditions. Here is the failure-mode contrast for series vs. shunt element faults:
| Component Fault | Circuit State | Resulting $V_{out}$ | Hazard Level & Mitigation |
|---|---|---|---|
| $C_1$ (Series) Shorts | Low impedance path to mains | 120VAC (Full Mains) | Catastrophic. Destroys MCU. Mitigation: Use X2 caps which fail open, not short. |
| $C_1$ (Series) Opens | Open circuit | 0V | Safe. System reads zero; triggers a 'sensor disconnected' software fault. |
| $C_2$ (Shunt) Shorts | Output shorted to ground | 0V | Safe. $R_{series}$ limits current. MCU reads zero. |
| $C_2$ (Shunt) Opens | Divider ratio destroyed | ~15V AC | Dangerous. The 1M$\Omega$ and 100k$\Omega$ bleed resistors form a new resistive divider, passing ~15V to the MCU pin. Mitigation: Add a 3.3V TVS diode or Schottky clamping diodes at the MCU pin. |
Step-by-Step Breadboard and Bench Testing
Never plug a newly breadboarded mains circuit directly into the wall. Follow this progressive verification sequence to protect your test gear and your life.
- Low-Voltage AC Injection: Connect a function generator to $V_{in}$ and GND. Set it to 60Hz, 10Vpp sine wave. Measure Node 2 with an oscilloscope. You should see ~147mVpp. This verifies the capacitance ratio without risk.
- Verify Bleed Resistors: Disconnect power. Charge $C_1$ momentarily with a 9V battery, then remove the battery. Use a multimeter to watch the voltage across $C_1$ decay. It must drop below 5V within 0.2 seconds.
- Variac Ramp-Up: Connect the circuit to a Variac (variable autotransformer) and an isolation transformer. Slowly ramp the AC voltage from 0V to 30VAC. Monitor the ESP32 ADC serial output to ensure the software RMS calculation tracks the multimeter's True-RMS reading.
- Fault Injection (Clamping Test): With the Variac at 30VAC, physically disconnect $C_2$ to simulate a shunt open-circuit. Verify that the 3.3V TVS diode clamps the voltage at the MCU pin and prevents the ADC from reading above 3.3V.
- Mains Verification: Once clamping and ratios are verified, connect to 120VAC mains via an isolation transformer. Monitor the thermal profile of $R_{bleed1}$ and $C_1$ for 15 minutes. They should remain at ambient temperature.
Final Component Selection & Default Recommendation
Do not substitute the series capacitor with generic ceramic discs or non-safety-rated film. For a 120VAC to 3.3V ESP32 sensing circuit, procure these exact component classes:
- $C_1$ (15nF Series): Vishay B32921C3153 or Cornell Dubilier 942C series (15nF, 305VAC X2 Metallized Polypropylene). Do not use Y-rated or standard film caps.
- $C_2$ (1.0$\mu$F Shunt): TDK/EPCOS B32529 (1.0$\mu$F, 63VDC/40VAC Metallized Polyester). Standard film is fine here as it is not directly across the mains lines.
- Clamping Diode: Nexperia PRTR5V0U2X (Dual TVS diode array) or two BAT54S Schottky diodes configured to clamp the signal between GND and the 3.3V rail.
- Resistors: 1M$\Omega$ and 100k$\Omega$ 1/4W Metal Film (1% tolerance to ensure predictable bleed times).
By locking in an X2 safety capacitor for the high-side drop and adding a TVS clamp for the silent $C_2$ open-circuit failure mode, this capacitive voltage divider provides a thermally invisible, highly reliable mains sensing front-end for modern 3.3V microcontrollers.
