Capacitive inductance is not a fundamental electrical property, but rather a practical engineering term for the parasitic Equivalent Series Inductance (ESL) inherent in the physical construction of real-world capacitors, which causes them to behave like inductors at high frequencies. When you place a physical capacitor on a PCB, you are not just placing pure capacitance; you are placing a series RLC circuit. This parasitic inductance changes your circuit by completely inverting the impedance profile above the component's self-resonant frequency (SRF), rendering the capacitor useless—or even harmful—for filtering high-frequency noise. Beginners commonly confuse this phenomenon with capacitive reactance (which predictably decreases as frequency rises) or assume 'capacitive inductance' is a distinct third component, rather than an unavoidable physical flaw born from the component's leads, vias, and internal electrode structure.

The Physical Reality of Parasitic ESL

In an ideal textbook circuit, a capacitor's impedance drops infinitely as frequency increases ($X_c = 1 / 2\pi fC$). In reality, current must physically enter one terminal, travel through the internal stacked metal electrodes, and exit the other terminal. That physical loop area creates a magnetic field, which is the exact definition of inductance.

The Spring-Mass Analogy: Think of a capacitor like a physical metal spring with mass. At low speeds, it acts like a pure spring (storing and releasing energy cleanly). But if you vibrate it fast enough, the physical mass of the metal (inductance) dominates the movement, and it stops acting like a spring entirely. In electronics, that 'vibration speed' is your signal frequency.

The smaller the physical package, the smaller the internal loop area, and the lower the ESL. This is why high-speed digital designs have migrated from 1206 and 0805 packages down to 0402 and 0201 packages—not just to save space, but to push the self-resonant frequency higher.

The Math: When a Capacitor Becomes an Inductor

To see how capacitive inductance ruins a decoupling network, let's run a worked numeric example using a standard decoupling capacitor.

The Component: A 100 nF (0.1 µF) X7R ceramic capacitor in a standard 0603 (1608 metric) package.
The Parasitics: Nominal Capacitance ($C$) = 100 nF. Typical ESL ($L$) = 0.5 nH.

The frequency where the capacitive reactance and inductive reactance cancel each other out is the Self-Resonant Frequency (SRF). Above this frequency, the inductive reactance ($X_L = 2\pi fL$) takes over, and the component's impedance begins to rise with frequency.

The formula for SRF is:

$$f_{SRF} = \frac{1}{2\pi\sqrt{L \times C}}$$

Plugging in our real-world values:

  • $L = 0.5 \times 10^{-9}$ H
  • $C = 100 \times 10^{-9}$ F
  • $L \times C = 50 \times 10^{-18}$
  • $\sqrt{L \times C} = 7.07 \times 10^{-9}$
  • $f_{SRF} = \frac{1}{2 \times 3.14159 \times 7.07 \times 10^{-9}} \approx 22.5 \text{ MHz}$
Critical Takeaway: At exactly 22.5 MHz, this 100nF capacitor provides maximum decoupling. At 50 MHz, 100 MHz, or 300 MHz, it acts as a 0.5 nH inductor. If your microcontroller's clock harmonic is 100 MHz, this capacitor is providing almost zero bypassing.

Where You Meet This in Practice

You will run headfirst into capacitive inductance in three specific scenarios:

  1. Power Distribution Networks (PDNs) for FPGAs and SoCs: Modern processors draw transient current spikes with harmonic frequencies well into the hundreds of megahertz. Relying solely on bulk 0.1 µF capacitors will result in massive voltage droop because their ESL blocks the high-frequency current delivery. You must parallel them with smaller 0402 10nF or 100pF caps to maintain a flat, low-impedance target across the frequency spectrum.
  2. Switching Power Supplies (Buck Converters): The switching node of a buck converter generates high $di/dt$ (change in current over time) edges. If the input bypass capacitor has high ESL, the inductance will interact with the fast switching edge to create severe high-frequency ringing ($V = L \frac{di}{dt}$), leading to EMI failures and potential MOSFET overvoltage stress.
  3. RF and Microwave Bypassing: In a 2.4 GHz WiFi circuit (like an ESP32-WROOM-32 antenna feed), a standard 100nF capacitor is effectively an open circuit or a resonant choke due to its ESL. RF designers use tiny 0201 10pF C0G/NP0 capacitors specifically because their SRF is tuned above 2.4 GHz.
Pro-Tip on Via Inductance: A standard 1.6mm thick PCB via adds roughly 0.5nH to 1.0nH of inductance. If your 0603 capacitor has 0.5nH of ESL, routing it through standard vias doubles the total inductance to 1.0nH. This drops your SRF by 30%. Always place high-frequency bypass capacitors on the same layer as the IC power pins, using via-in-pad or ultra-short traces to minimize loop area.

Decision Path: Beating Parasitic ESL in Your Next Design

Stop guessing your decoupling network. Use this decision tree to select the exact capacitor package and part number based on your target noise frequency.

Target Noise Frequency Required Package Size Dielectric / Value Concrete Part Pick (Murata)
< 10 MHz
(General bulk decoupling, audio, slow MCUs)		 0603 or 0805 X7R
100 nF - 1 µF		 GRM188R71H104KA93
(100nF, 50V, 0603)
10 MHz - 100 MHz
(Fast digital logic, standard switching regulators)		 0402 X7R
10 nF - 100 nF		 GRM155R71H104KE14
(100nF, 25V, 0402)
100 MHz - 500 MHz
(High-speed DDR, FPGAs, RF bypass)		 0201 C0G/NP0
10 pF - 1 nF		 GRM0335C1H100JA01
(10pF, 50V, 0201)
> 500 MHz
(GHz-class PDNs, EMI filtering)		 0603 3-Terminal (Feedthrough) X5R / Multilayer
1 µF		 NFM18PC105B1C3
(1µF, 16V, 3-Terminal)

Note: For frequencies above 500 MHz, standard 2-terminal capacitors fail entirely due to ESL. You must switch to 3-terminal feedthrough capacitors (like the NFM series), which route the signal through the capacitor internally, virtually eliminating the series inductance loop according to Murata's EMC design guidelines.

Frequently Asked Questions

Can I just put ten 0.1 µF capacitors in parallel to reduce ESL?

Yes and no. Placing identical capacitors in parallel does reduce the total equivalent ESL (just like resistors in parallel), but it creates a dangerous anti-resonance peak. When two capacitors of different values (or even the same value with slightly different PCB trace lengths) are placed in parallel, their impedance curves intersect. At that intersection, they form a parallel LC tank circuit, creating a massive spike in impedance. It is always better to use a single, physically smaller capacitor (like an 0402) with a higher SRF than to parallel multiple large 0603 capacitors.

Does the PCB trace length matter more than the capacitor's internal ESL?

Absolutely. A 1mm wide PCB trace on standard FR4 material adds roughly 1 nH of inductance per millimeter of length. If you place a low-ESL 0201 capacitor but route it with a 5mm trace to the IC pin, you have added 5 nH of trace inductance to the capacitor's 0.2 nH internal ESL. The physical layout completely dominates the component's datasheet specs. Keep traces as short and wide as physically possible, or use via-in-pad placement directly under the component.

How do I measure the actual capacitive inductance on my board?

You cannot measure it accurately with a standard handheld LCR meter, as they typically test at 1 kHz or 100 kHz—far below the SRF. To measure the true impedance profile including ESL and via inductance, you need a Vector Network Analyzer (VNA) to perform a 2-port shunt-through measurement from 10 MHz up to 3 GHz, or use an oscilloscope with a high-bandwidth active probe to measure the power rail impedance via a step-load transient response test. For practical design, rely on the manufacturer's S-parameter files and simulate your PDN in software like Keysight ADS or Altair.

For a deeper dive into the physics of decoupling and high-frequency parasitics, the Analog Devices MT-101 Tutorial on Decoupling Techniques remains the industry-standard reference for mapping impedance targets to physical capacitor selections.