The Capacitive Divider Topology and Node Definitions
A capacitive divider scales down an alternating current (AC) voltage using the reactive impedance of series capacitors rather than the resistive dissipation of resistors. Because ideal capacitors do not dissipate real power (watts), this topology is the default choice for high-voltage AC sensing where a resistive divider would overheat or require massive, expensive wirewound components.
The basic topology consists of two capacitors in series between the input source and ground:
- Node Vin: The high-voltage AC source (e.g., 120VAC mains).
- C1 (Top Capacitor): The series impedance element. It drops the bulk of the voltage.
- Node Vout: The midpoint tap where the scaled-down AC signal is measured.
- C2 (Bottom Capacitor): The shunt impedance element to ground.
- Node GND: The circuit common/ground reference.
Unlike a resistive divider where the output ratio depends on R2 / (R1 + R2), the capacitive divider ratio is inverted because capacitive reactance (XC) is inversely proportional to capacitance (XC = 1 / 2πfC). The smaller capacitor drops the larger voltage. The transfer function is:
Vout = Vin × [ C1 / (C1 + C2) ]
Capacitive vs. Resistive: The Decision Matrix
Why choose a capacitive divider over a standard resistive network? The decision hinges on frequency, voltage level, and power dissipation constraints. Use the decision tree below to lock in your topology.
| Application Condition | Topology Pick | Why This Wins |
|---|---|---|
| DC or steady-state low-frequency (<1Hz) measurement | Resistive Divider | Capacitors block DC; reactance approaches infinity at 0Hz. |
| High-voltage AC sensing (>50V RMS, e.g., mains) | Capacitive Divider | Zero real power dissipation. A resistive divider here would burn watts and require high-voltage rated, expensive resistors. |
| High-frequency RF (>10MHz) signal attenuation | Capacitive Divider | Resistors exhibit parasitic parallel capacitance and series inductance at RF. C0G/NP0 capacitors remain highly predictable. |
| Low-voltage AC audio coupling (20Hz - 20kHz) | Resistive Divider | Capacitors in the audio path require large, expensive film values to avoid altering the low-frequency phase response. |
The Default Recommendation: If you are measuring >50VAC for a microcontroller ADC or building an RF probe, pick the capacitive divider. If you are measuring DC or low-voltage audio, pick resistive.
Component Selection and 120VAC Design Walkthrough
Let's design a concrete capacitive divider to step down 120VAC (60Hz) mains to a safe level for an ESP32 ADC (3.3V max, but we will target 2.8V peak to leave headroom for transients).
Step 1: Calculate the Required Ratio
120VAC RMS has a peak voltage of 120 × √2 = 169.7V. We want a peak output of 2.8V.
Ratio = 2.8 / 169.7 = 0.0165.
Using the formula: C1 / (C1 + C2) = 0.0165. This means C2 must be approximately 59.5 times larger than C1.
Step 2: Pick Real Component Values
Let's choose C1 = 8.2nF.
C2 = 8.2nF × 59.5 = 487.9nF. The closest standard E12 value is 470nF.
Recalculating with 470nF: Ratio = 8.2 / (8.2 + 470) = 0.0171.
Actual Vout_peak = 169.7V × 0.0171 = 2.90V. This is perfect for a 3.3V ADC.
Step 3: Select the Dielectric and Voltage Ratings (Crucial)
This is where most hobbyists fail. You cannot use standard X7R or Y5V ceramics for C1. X7R capacitors exhibit a severe voltage coefficient—their capacitance can drop by 50% or more when subjected to high DC or AC bias, completely ruining your divider ratio. Furthermore, X7R ceramics are piezoelectric; they will act as microphones, injecting acoustic noise into your AC sensing circuit.
- C1 (8.2nF) Pick: Metallized Polyester Film (e.g., EPCOS/TDK B32529 series) or C0G/NP0 Ceramic. It must withstand the 170V peak plus a safety margin. Select a 630V DC rated film capacitor. Film caps have no voltage coefficient and self-heal upon minor dielectric breakdown.
- C2 (470nF) Pick: Standard 50V X7R Ceramic (e.g., Murata GRM series). Since C2 only sees ~3V, the voltage coefficient is negligible, and X7R provides high capacitance in a tiny 0805 package.
Step 4: Add Bias and Bleeder Networks
A purely capacitive divider has infinite DC impedance. The ESP32 ADC sampling capacitor will charge the node and cause erratic readings. You must provide a DC path.
- Bleeder Resistor (R1): Place a 1MΩ, 250V rated resistor in parallel with C1. This safely discharges the high-voltage film cap when the mains is unplugged.
- Pulldown Resistor (R2): Place a 10kΩ resistor in parallel with C2. This provides the necessary DC bias path for the ADC sample-and-hold circuit without significantly loading the AC signal (10kΩ is vastly smaller than the ~564Ω reactance of C2 at 60Hz).
- Clamp Diodes: Add a 3.3V Zener diode or TVS diode (e.g., Littelfuse SMAJ3.3A) at Vout to protect the MCU from mains surges.
Failure Modes: What Breaks at the Extremes?
When designing for mains-adjacent circuits, you must assume components will eventually fail. Here is the behavior matrix for single-point failures in this topology.
| Failure Mode | Circuit Behavior | Consequence & Mitigation |
|---|---|---|
| C1 Shorts | Vout connects directly to Vin. | Catastrophic. 170V peak hits the MCU ADC, destroying the silicon and posing a shock hazard. Mitigation: Use a high-voltage rated film cap for C1 which typically fails open, not short. Add a fast-blow fuse or spark gap at Vout. |
| C1 Opens | Vout loses connection to Vin. | Vout drops to 0V (held by R2). The MCU reads zero voltage. Safe failure mode. |
| C2 Shorts | Vout is pulled directly to GND. | Vout = 0V. The MCU reads zero. C1 now drops the full mains voltage. Safe, provided C1's voltage rating isn't exceeded (which it won't be, as it's rated for 630V). |
| C2 Opens | Vout loses connection to GND. | Vout floats up to Vin through C1. Dangerous. The MCU will be destroyed. Mitigation: The 3.3V TVS clamp diode at Vout will short the node, blowing the upstream protection or clamping the voltage to save the MCU. |
Breadboard Testing and Verification Protocol
Do not plug a freshly designed capacitive divider directly into the wall. Mains voltage on a solderless breadboard is an arc-flash and electrocution hazard. Follow this stepped verification protocol to validate your math and component choices safely.
- Assemble the Low-Voltage Prototype: Populate C1, C2, R1, R2, and the TVS diode on the breadboard. Leave Vin disconnected.
- Inject a Safe Test Signal: Connect a function generator to Vin. Set it to output a 60Hz sine wave at 10V peak-to-peak (approx 3.5V RMS). Connect the generator's ground to the circuit GND.
- Measure the Baseline: Connect your oscilloscope probes. Channel 1 on Vin, Channel 2 on Vout. Verify that Vout is a clean sine wave. With a 10Vpp input, your 0.0171 ratio should yield exactly 171mV peak-to-peak at Vout.
- Verify Phase Shift: Use the scope's cursor function to measure the time delay between the zero-crossings of Vin and Vout. Because of the 10kΩ pulldown resistor (R2) interacting with C2, you will see a slight phase lead. Ensure this phase shift is acceptable for your specific application (e.g., zero-cross detection vs. simple RMS amplitude measurement).
- Test the Extremes: With the function generator still at 10Vpp, temporarily remove C2 to simulate an open-circuit failure. Verify that the TVS diode clamps Vout safely and the waveform flattens at 3.3V rather than spiking to 10V.
- Scale Up to Isolated Mains: Once the low-voltage math is proven, move the circuit to a soldered perfboard (never breadboard mains). Power it through a 1:1 isolation transformer with a 100mA current limit. Measure the AC RMS voltage at Vout with a true-RMS multimeter. It should read approximately 2.05V RMS (2.90V peak / √2).
By forcing the design through a low-voltage function generator test first, you validate the AC capacitance reactance math without risking your test equipment or your life. When selecting your final components, always prioritize C0G/NP0 or film dielectrics for the high-voltage leg, and never omit the DC bias pulldown resistor.
