A capacitive circuit designed for PWM-to-DC smoothing relies on the energy-storage properties of capacitors to integrate a digital square wave into a steady analog voltage. If you are trying to drive an analog sensor input, a legacy 0-10V industrial controller, or a DC motor from a microcontroller's digital pulse-width modulation (PWM) pin, a single capacitor won't cut it. The optimal solution is a two-stage passive RC low-pass filter. This topology provides a -40dB/decade roll-off, aggressively killing switching ripple while maintaining a predictable DC output.
Topology Description and Node Labels
To convert a 5V PWM signal into a clean 0-5V DC analog signal, we use a cascaded two-stage RC network. A single-stage RC filter only provides a -20dB/decade attenuation, which often leaves 100mV to 200mV of high-frequency sawtooth ripple on the output. Cascading two stages doubles the attenuation slope to -40dB/decade.
The circuit consists of four primary nodes:
- VIN: The raw PWM input from the microcontroller (e.g., Arduino Pin 9).
- N1: The interstage node connecting the first resistor to the first capacitor and the second resistor.
- N2 (VOUT): The final output node connecting the second resistor to the second capacitor and your load.
- GND: The common ground reference shared by the microcontroller, the capacitors, and the load.
The signal flows from VIN through resistor R1 to N1. At N1, capacitor C1 shunts high-frequency AC components to GND. The filtered signal then passes through resistor R2 to N2, where capacitor C2 performs a second round of AC shunting. The resulting DC voltage is read at VOUT.
Design Walkthrough: Picking Real Component Values
Let's design this capacitive circuit for an Arduino Uno. According to the Arduino analogWrite() reference, pins 5 and 6 operate at approximately 490Hz, while pins 3, 9, 10, and 11 operate at 980Hz. We must design for the worst-case scenario: 490Hz.
To effectively eliminate the fundamental ripple frequency, the filter's cutoff frequency ($f_c$) should be at least one-tenth of the PWM frequency. Target $f_c \approx 15\text{ Hz}$.
The formula for the cutoff frequency of an RC stage is:
$$f_c = \frac{1}{2 \pi R C}$$
If we select R1 = 10kΩ and C1 = 10µF, the math yields:
$$f_c = \frac{1}{2 \pi \times 10,000 \times 0.00001} \approx 1.59\text{ Hz}$$
We duplicate these values for the second stage: R2 = 10kΩ and C2 = 10µF. This pushes the effective system cutoff well below our 15Hz target, guaranteeing a flat DC line.
Do not use Y5V or Z5U ceramic capacitors for C1 and C2. These dielectrics suffer from severe DC bias derating—a 10µF Y5V capacitor might drop to 2µF when 5V is applied across it, shifting your cutoff frequency unpredictably. Use X7R MLCC ceramics or standard aluminum electrolytic capacitors. For deep technical context on how dielectrics store and release charge, refer to the Analog Devices guide on dielectric absorption.
Behavior Matrix and Extreme Failure Modes
Understanding how a capacitive circuit reacts to component drift or catastrophic failure is critical for debugging. The table below maps specific element changes to their observable effects on VOUT.
| Element Changed | Direction of Change | Effect on VOUT (DC Level & Ripple) |
|---|---|---|
| R1 or R2 | Increases (e.g., +20%) | DC level remains accurate, but settling time increases; VOUT responds slower to PWM duty cycle changes. |
| C1 or C2 | Decreases (e.g., dries out) | DC level remains accurate, but high-frequency ripple amplitude increases significantly. |
| Load Impedance | Decreases (heavy load) | DC level drops below expected value due to voltage division between R2 and the load. |
| PWM Frequency | Decreases (e.g., to 50Hz) | Ripple increases because the 50Hz fundamental is closer to the 1.59Hz cutoff frequency. |
What Breaks at the Extremes?
Shorted Capacitor (C1 or C2 shorts to GND): If C2 shorts, VOUT becomes a hard 0V. If C1 shorts, node N1 is pulled to ground. The microcontroller's PWM pin will attempt to drive 5V through R1 into a dead short. Because R1 is 10kΩ, the current is limited to 0.5mA ($I = V/R = 5/10000$), which is well within the 20mA absolute maximum rating of an ATmega328P GPIO pin. The microcontroller survives, but VOUT reads 0V.
Open Capacitor (C1 or C2 loses connection): If C2 opens, the second stage loses its filtering capability. The circuit degrades to a single-stage RC filter. You will see a massive 100mV+ sawtooth ripple on your oscilloscope at VOUT. If C1 opens, N1 passes the raw 5V square wave directly through R2 into C2. C2 will attempt to filter the raw square wave alone, resulting in severe ripple and a delayed settling time.
Why This Topology Over the Alternatives?
When smoothing PWM, makers typically choose between a passive RC network, an LC (inductor-capacitor) filter, or an active op-amp filter. Here is why the two-stage capacitive circuit wins for general-purpose microcontroller applications.
| Criteria | Two-Stage RC (Capacitive) | LC Filter (Inductor + Cap) | Active Op-Amp Filter |
|---|---|---|---|
| Component Cost | ~$0.10 (Resistors + Caps) | ~$1.50+ (Shielded inductors are pricey) | ~$0.80 (Op-amp + precision passives) |
| Resonance Risk | None (Overdamped by design) | High (Can ring and overshoot if Q is high) | Low (Depends on compensation) |
| Output Impedance | High (R1+R2 = 20kΩ) | Very Low (Ideal for high current loads) | Very Low (Driven by op-amp output) |
| Board Space | Minimal (0805 SMD or small DIP) | Large (Inductors are bulky) | Moderate (Requires SOIC/DIP IC) |
Choose the RC capacitive circuit when: Your load is high-impedance (e.g., feeding an ADC input, an op-amp buffer, or a MOSFET gate) and you need a cheap, resonance-free solution.
Choose an LC filter when: You are driving a low-impedance, high-current load like a DC motor or a high-power LED array, where the 20kΩ output impedance of an RC filter would cause unacceptable voltage sag.
Step-by-Step Breadboard Testing Protocol
Do not just wire this up and trust a multimeter. Follow this exact sequence to verify the capacitive circuit's behavior on the bench.
- De-energize and Wire: With the microcontroller powered off, insert R1, R2, C1, and C2 into the breadboard. Ensure the ground rails for the microcontroller and the capacitors are physically bridged. Mistake to avoid: Floating grounds between the MCU and the filter will result in erratic VOUT readings.
- Static DMM Check: Before applying power, set your digital multimeter (DMM) to resistance mode. Measure between VOUT and GND. You should read approximately 20kΩ (the series sum of R1 and R2, assuming C1/C2 are uncharged). If you read 0Ω, you have a shorted capacitor or a wiring error.
- Baseline DC Measurement: Power the microcontroller. Upload a sketch that outputs a 50% duty cycle PWM (e.g.,
analogWrite(9, 127);). Set the DMM to DC Volts and probe VOUT. It should read 2.45V to 2.55V. (It won't be exactly 2.50V due to the MCU's internal MOSFET voltage drops and DMM averaging). - Oscilloscope Ripple Verification: Connect a 10x oscilloscope probe to VOUT. Set the scope to AC+DC coupling, 1V/div vertical scale, and 2ms/div horizontal scale. Trigger on the rising edge. You should see a flat line. If you see a 490Hz or 980Hz sawtooth wave exceeding 50mV peak-to-peak, your capacitors are either the wrong value, wired incorrectly, or suffering from extreme ESR.
- Step Response Test: Change the code to alternate between
analogWrite(9, 0);andanalogWrite(9, 255);every 1000ms. Observe the scope. The VOUT trace should show smooth, exponential RC charging and discharging curves, taking approximately 200ms to settle to the new DC level.
Frequently Asked Questions
Why does my capacitive circuit output a lower voltage than expected under load?
This is caused by impedance loading. The two-stage RC filter has a Thevenin equivalent output impedance roughly equal to R1 + R2 (20kΩ in our design). If you connect a load with a resistance of 100kΩ to VOUT, it forms a voltage divider with the filter's output impedance. The 5V signal will drop to roughly 4.16V ($5V \times \frac{100k}{100k + 20k}$). To fix this, either decrease the values of R1 and R2 (and proportionally increase C1 and C2 to maintain the same cutoff frequency) or buffer the VOUT node with a unity-gain op-amp like the LM358 or MCP6002.
Can I use a polarized electrolytic capacitor in this capacitive circuit?
Yes, but with strict conditions. Polarized aluminum electrolytic capacitors require a positive DC bias voltage across their terminals at all times. In a PWM smoothing circuit, the DC bias is always positive (between 0V and 5V), which is safe. However, if the PWM signal is turned off (0V) and the circuit is subjected to external negative transients, the capacitor's dielectric oxide layer can break down, leading to high leakage current or catastrophic venting. If your application involves bipolar signals (swinging above and below ground) or AC coupling, you must use non-polarized film capacitors or bipolar electrolytics. For standard 0-5V DC smoothing, standard polarized electrolytics wired with the anode (+) toward the resistors and cathode (-) to GND are perfectly safe and cost-effective.
How do I calculate the settling time for this capacitive circuit?
Settling time dictates how fast your analog output can respond to a change in the PWM duty cycle. For a single RC stage, the time constant ($\tau$) is $R \times C$. A capacitor is considered fully charged (to within 99.3%) after $5\tau$. In our two-stage design, the stages interact, but a practical engineering approximation for the 10% to 90% step response settling time is roughly $4.4 \times R_{eq} \times C_{eq}$. With R = 10kΩ and C = 10µF, $\tau = 0.1$ seconds. Therefore, expect the circuit to take approximately 0.4 to 0.5 seconds to fully settle when transitioning from 0V to 5V. If your application requires faster settling (e.g., audio synthesis or fast motor control), you must lower the R and C values proportionally, accepting higher component costs or larger physical footprints.
