The series capacitance formula dictates that connecting capacitors in series reduces the total equivalent capacitance while increasing the overall voltage rating. If your DC bus voltage exceeds the maximum rating of readily available, cost-effective single capacitors, this topology is your primary design tool. For a 700V solar inverter DC link, you do not hunt for a rare 800V capacitor; you stack two standard 450V units in series and apply the inverse sum formula to calculate the resulting filter capacitance.
Topology and the Series Capacitance Formula
When wiring capacitors in series, the physical topology creates a voltage divider network. Consider a two-capacitor series string:
- Node A (Input / V_in): The positive high-voltage DC bus connection, tied to the positive lead of Capacitor 1 (C1).
- Node B (Midpoint / V_mid): The junction where the negative lead of C1 connects to the positive lead of Capacitor 2 (C2). This node must never be left floating in high-voltage electrolytic designs.
- Node C (Ground / GND): The negative lead of C2, tied to the system ground or negative DC bus.
The governing capacitance formula in series for two components is:
C_eq = (C1 × C2) / (C1 + C2)
If C1 and C2 are identical (e.g., both 100µF), the equivalent capacitance is exactly half of a single unit (50µF), while the theoretical voltage rating doubles. Unlike resistors in series (which add up), series capacitors behave like resistors in parallel. This inverse relationship means you must over-specify the individual capacitance values to achieve your target system capacitance.
Decision Path: Series vs. Parallel vs. Single
Choosing a capacitor topology is a binary decision driven by voltage limits and physical footprint. Use this decision matrix to lock in your configuration:
| Design Constraint | Optimal Topology | Why This Wins |
|---|---|---|
| DC Bus > 500V, standard cap ratings max at 450V/500V | Series | Avoids custom, expensive, or physically massive high-voltage single cans. |
| Need higher ripple current handling and larger µF | Parallel | Capacitance adds linearly; ESR drops, distributing thermal load. |
| Need specific non-standard value (e.g., 15µF) | Series/Parallel Combo | Allows tuning using standard E12/E24 series values. |
| High-frequency decoupling on a 3.3V logic rail | Parallel (Mixed Values) | Combines bulk low-frequency storage with high-frequency MLCC bypass. |
Design Walkthrough: Building an 800V DC Bus Filter
Let us design a filter for an 800V nominal DC bus (max 850V transient) requiring 50µF of bulk capacitance. We will use two 100µF, 450V snap-in electrolytics.
1. Calculate Equivalent Capacitance
Using the formula: C_eq = (100 × 100) / (100 + 100) = 50µF. The voltage rating theoretically becomes 900V, safely covering our 850V transient peak.
2. The Leakage Current Imbalance Problem
Electrolytic capacitors are not perfect. They exhibit internal leakage current, which varies from part to part even within the same manufacturing batch. If C1 has lower leakage than C2, C1 will charge to a higher voltage. In an 850V system, Node B could drift to 500V, leaving C1 with 350V and C2 with 500V. C2 exceeds its 450V rating, its dielectric breaks down, and it vents violently.
3. Sizing the Balancing Resistors
To force equal voltage division at Node B, we place high-value resistors in parallel with each capacitor. According to capacitor network tutorials, these bleed resistors must draw a current significantly higher than the worst-case capacitor leakage current.
- Cap Leakage Spec: Standard formula is I_leak = 0.003 × C × V (in µA). For 100µF at 450V, max leakage is ~135µA.
- Resistor Current Target: We want the resistor to draw at least 5x to 10x the max leakage to dominate the voltage divider. Let us target 2mA through the resistors.
- Resistor Value: R = V_half / I_target = 425V / 0.002A = 212,500Ω.
- Concrete Pick: Use standard 220kΩ, 2-Watt metal film resistors. The 2W rating is mandatory; a standard 1/4W resistor will overheat and fail open at 425V (P = V²/R = 425² / 220,000 = 0.82W, so 2W provides a safe thermal margin).
Failure Modes: What Breaks at the Extremes?
Understanding how series strings fail is critical for system-level protection. Here is the behavior contrast when elements fail:
| Failure Event | Node B (Midpoint) Behavior | System Consequence |
|---|---|---|
| C1 Fails Short | Pulls to V_in (800V) | C2 instantly absorbs the full 800V bus. C2 exceeds 450V rating, dielectric ruptures, catastrophic venting or explosion. System shorts out. |
| C1 Fails Open | Floats unpredictably | Filter capacitance drops to near zero. High-frequency ripple destroys downstream switching MOSFETs/IGBTs. No immediate explosion, but secondary failure follows. |
| Balancing Resistor R1 Fails Open | Slowly drifts toward GND or V_in | Voltage division relies entirely on mismatched leakage currents. Over hours or days, one cap will silently overvolt and degrade, shortening lifespan. |
| Node B Accidentally Grounded | Forced to 0V | C1 takes full 800V (fails). C2 is bypassed. Immediate catastrophic failure of C1. |
Step-by-Step Breadboard Verification
Do not use a standard 0.1-inch solderless breadboard for this test. Solderless breadboards are typically rated for 60V maximum; 800V will arc across the internal metal clips, causing a fire or lethal shock. Use a high-voltage perfboard, screw terminal blocks, or a dedicated high-voltage test jig.
Tools Required: LCR meter, benchtop DC power supply (capable of 50V for initial test), high-voltage probe for multimeter, 2W 220kΩ resistors, two 100µF 450V caps.
- Verify Dead and Discharge: Before handling, short the leads of both capacitors with a 1kΩ 5W power resistor to ensure no residual charge remains. Never short them directly with a screwdriver, as the high dV/dt can damage the internal foil connections.
- Baseline Component Measurement: Use your LCR meter to measure C1 and C2 individually at 120Hz. Record the exact values (e.g., C1 = 108µF, C2 = 96µF) and their Dissipation Factor (DF). Reject any cap with a DF > 0.15.
- Assemble the String: Wire C1 and C2 in series on the terminal block. Solder the 220kΩ balancing resistors directly across the leads of C1 and C2. Keep the physical leads short to minimize parasitic inductance.
- Verify Equivalent Capacitance: Measure across Node A and Node C with the LCR meter. You should read approximately 50µF (adjusted slightly based on your baseline mismatch). If it reads infinite or open, check your series junction.
- Low-Voltage Midpoint Test: Connect the bench supply across Node A and Node C. Set the supply to 50V. Measure the voltage at Node B relative to Node C. It should read exactly 25V (±0.5V). This confirms the 220kΩ resistors are successfully dominating the voltage division and masking any low-voltage leakage mismatch.
- Scale and Monitor: Only after the 50V test passes should you integrate the string into the high-voltage circuit. Upon first full-power application (800V), monitor Node B with a high-voltage differential probe for the first 10 minutes to ensure the midpoint stabilizes at 400V ± 20V as the capacitors reach their operating temperature and leakage currents shift.
Series capacitor networks are highly effective for high-voltage DC links, provided you respect the math and the physics of leakage current. Never omit the balancing resistors, and always verify the midpoint voltage before scaling up to full bus voltage.
