How to Calculate RTD Resistance to Temperature for Closed-Loop Thermal Management

To calculate RTD (Resistance Temperature Detector) resistance to temperature for a standard Pt100 or Pt1000 sensor, you use the Callendar-Van Dusen (CVD) equation. For the 0°C to 150°C range typical in electronics thermal management, the linear approximation R(T) = R₀(1 + αT) is highly effective. For a Pt100 sensor (R₀ = 100Ω) with a standard European curve (α = 0.00385), the resistance increases by exactly 0.385 Ω per °C. At 85°C, the resistance is 132.72 Ω.

But knowing the math is only half the battle. In closed-loop thermal management for high-power electronics—like SiC MOSFETs or IGBT modules—the RTD is your primary feedback mechanism. If your microcontroller misinterprets that 132.72 Ω reading, your fan curve triggers late, or your thermal shutdown fires unnecessarily. This guide bridges the gap between raw RTD sensor math and physical thermal path engineering, showing you exactly how to size your heatsinks and interpret derating curves based on accurate temperature data.

The Math: How to Calculate RTD Resistance to Temperature

While the linear approximation works for quick bench checks, precision thermal loops require the full Callendar-Van Dusen equation to account for the slight non-linearity of platinum at temperature extremes. According to Omega Engineering's RTD standards, the CVD equation for temperatures above 0°C is:

R(T) = R₀ [1 + AT + BT²]

• R₀: Resistance at 0°C (100Ω for Pt100, 1000Ω for Pt1000)
• A: 3.9083 × 10^-3 °C^-1
• B: -5.775 × 10^-7 °C^-2

Thermal Path Math: From Junction to Ambient (R_θ)

Once your MCU accurately calculates the case temperature (T_c) from the RTD resistance, you must determine the actual silicon junction temperature (T_j). You cannot measure T_j directly; you must calculate it using thermal resistance (R_θ) values provided in the semiconductor datasheet, following JEDEC JESD51-1 standards for IC thermal measurement.

The fundamental thermal path equation is:

T_j = T_c + (P_D × R_θJC)

Where:

• T_j: Junction temperature (the silicon die)
• T_c: Case temperature (where your RTD is physically mounted)
• P_D: Power dissipation in Watts
• R_θJC: Thermal resistance from Junction to Case (°C/W)

Worked Example: You are driving an IGBT module dissipating 45W. The datasheet specifies an R_θJC of 0.8 °C/W. Your RTD, epoxied to the center of the module baseplate, calculates a case temperature of 75°C.
T_j = 75 + (45 × 0.8) = 111°C.

Heatsink Selection and Derating Curves

Let's say our 111°C junction temperature is too close to our 125°C reliability limit, and we need to drop it. We must calculate the required heatsink-to-ambient thermal resistance (R_θSA).

The full thermal path equation is:
R_θJA = R_θJC + R_θCS + R_θSA

Assuming a maximum ambient temperature (T_a) of 40°C inside the enclosure, and a target T_j of 110°C:
Max R_θJA = (110°C - 40°C) / 45W = 1.55 °C/W.

Subtracting the known resistances:
R_θJC (Junction-to-Case) = 0.8 °C/W
R_θCS (Case-to-Sink, using a 0.2 °C/W phase-change thermal pad) = 0.2 °C/W
Required R_θSA (Sink-to-Ambient) = 1.55 - 0.8 - 0.2 = 0.55 °C/W.

Interpreting the Derating Curve

Heatsink manufacturers provide derating curves showing R_θSA versus airflow in Linear Feet per Minute (LFM). A massive extruded heatsink might have an R_θSA of 1.2 °C/W in natural convection (0 LFM), but drop to 0.4 °C/W at 400 LFM.

The Concrete Pick: For this 45W application in a 40°C ambient enclosure, mount the Aavid Thermalloy 7022B-MTG using a Honeywell PTM7950 phase-change TIM. Pair it with a Sunon MF40101VX 40mm fan pushing roughly 200 LFM across the fins. This yields an R_θSA of 0.45 °C/W, dropping your junction temperature to a safe 105.5°C.

Failure Signatures of Thermal Stress

What happens when your RTD loop fails to catch a thermal runaway, or your heatsink calculation ignored enclosure stagnation? According to Texas Instruments' thermal design guidelines, thermal stress manifests in specific physical failure modes:

• Die Attach Fatigue (Solder Cracking): Repeated thermal cycling (e.g., turning a 50A load on and off) causes the silicon die and copper baseplate to expand at different rates. The solder layer cracks, creating voids. This increases R_θJC over time. Signature: Your RTD reads a lower case temperature, but the silicon is actually running hotter because the heat can no longer reach the case.
• TIM Pump-Out: If you use standard thermal grease instead of phase-change material or thermal pads, the expansion/contraction cycle literally pumps the grease out from the center of the IGBT module, leaving a dry spot. Signature: Gradual increase in case temperature over 6-12 months of operation.
• Wire Bond Lift-Off: Extreme T_j spikes melt or detach the aluminum wire bonds connecting the die to the terminals. Signature: Sudden, catastrophic open-circuit failure, often accompanied by a localized arc flash inside the module.

Decision Path: Sizing Your Thermal Loop

Stop guessing your cooling strategy. Use this decision tree to terminate your thermal design process with a concrete hardware pick based on your RTD-monitored power dissipation.

By accurately calculating your RTD resistance to temperature, you close the loop between physical silicon limits and firmware control. Don't rely on the semiconductor's internal thermal shutdown diode—it's notoriously inaccurate and placed too far from the hot spot. Epoxied external RTDs, proper R_θ math, and phase-change TIMs are the difference between a prototype that burns up on the bench and a product that survives a 10-year field deployment.