To calculate input impedance ($Z_{in}$), divide the small-signal AC voltage at the input node by the AC current flowing into it ($Z_{in} = V_{in} / I_{in}$). In practical signal integrity and noise control, you calculate this value to determine if a node is high-impedance (making it an antenna for capacitive and radiated noise) or low-impedance (making it susceptible to conductive ground loops and reflections). Getting this number right is the difference between a clean 10 MHz clock signal and a ringing, EMI-fried mess.
The Data-Driven Guide to Input Impedance and Noise Coupling
Before you reach for a soldering iron, you must identify which coupling path is dominant in your specific circuit stage. High-impedance nodes act like capacitors waiting to be charged by stray electric fields (capacitive coupling) or radio frequency interference (radiated coupling). Low-impedance nodes are largely immune to electric fields but will readily sink noise currents from shared ground paths (conductive coupling).
The table below maps common input stages to their typical impedance values, the dominant noise coupling path you must defend against, and their relative vulnerability.
| Circuit Stage / Component | Typical $Z_{in}$ (AC/DC) | Dominant Coupling Path | Noise Vulnerability |
|---|---|---|---|
| BJT Common Emitter | $\beta \times r_e$ (1kΩ - 5kΩ) | Conductive (Ground bounce) | Moderate |
| MOSFET Gate (AC) | $1 / (2\pi f C_{iss})$ (Drops to <100Ω at HF) | Capacitive (Crosstalk / dV/dt) | High at switching edges |
| Op-Amp (Bipolar Input) | 100kΩ to 2MΩ (Differential) | Conductive & Radiated | Moderate |
| Op-Amp (JFET/CMOS Input) | >$10^{12}$ Ω (DC), Capacitive at AC | Capacitive (EMI Rectification) | Very High |
| 50Ω Coax Termination | 50Ω ±1% (Resistive) | Conductive (Ground loops) | Low (if properly terminated) |
| 10x Oscilloscope Probe | 10MΩ || ~12pF | Capacitive (Loading effects) | High above 50 MHz |
As noted in Analog Devices' Rarely Asked Questions on input impedance, CMOS and JFET op-amps present a deceptive trap: while their DC impedance is practically infinite, their AC impedance plummets at high frequencies due to parasitic input capacitance, making them highly susceptible to RF rectification if left unfiltered.
Calculating $Z_{in}$ for Common Circuit Topologies
Abstract formulas do not help when you are debugging a noisy PCB. Here is how to calculate $Z_{in}$ with real-world numbers for the components you actually stock in your bench drawers.
1. The Bipolar Junction Transistor (BJT)
For a common-emitter amplifier, the input impedance looking into the base is approximately $Z_{in} \approx \beta \times r_e$, where $r_e$ is the dynamic emitter resistance.
Worked Example: You bias a 2N3904 transistor with an emitter current ($I_E$) of 1 mA.
$r_e = 26mV / I_E = 26mV / 1mA = 26\Omega$.
Assuming a typical $\beta$ (hFE) of 150 at this operating point:
$Z_{in} = 150 \times 26\Omega = 3,900\Omega$ (3.9 kΩ).
At 3.9 kΩ, this node is relatively low impedance. It will ignore stray capacitive crosstalk from a nearby SPI bus, but it will pick up conductive noise if your ground plane is fractured.
2. The MOSFET Gate (The High-Frequency Trap)
Hobbyists often assume MOSFET gates are purely high-impedance because their DC gate current is essentially zero. This is a fatal error in signal integrity. At AC, the input impedance is dictated by the total input capacitance ($C_{iss}$).
Worked Example: You are driving an IRF540N power MOSFET with a 1 MHz PWM signal. The datasheet lists $C_{iss} \approx 1800pF$.
$Z_{in} = X_c = 1 / (2\pi \times f \times C_{iss}) = 1 / (2\pi \times 10^6 \times 1800 \times 10^{-12}) \approx 88\Omega$.
At 1 MHz, your 'high impedance' gate is actually an 88-ohm load. If your gate driver cannot source the required peak current ($I = V / Z_{in} = 12V / 88\Omega \approx 136mA$), your switching edges will slow down, causing massive conductive heat and radiated EMI.
3. Operational Amplifiers
Op-amp input impedance is split into differential and common-mode specifications. For a standard bipolar op-amp like the LM358, the differential input impedance is roughly 100 kΩ to 300 kΩ. However, for precision DC measurements, you must calculate the effective impedance created by your feedback network. If you use 100 kΩ feedback resistors on a CMOS op-amp (like the TLC27L2), the 100 kΩ resistors dominate the node impedance, not the op-amp's internal $10^{12}\Omega$ FET gates. Always calculate the Thevenin equivalent resistance of your external passive network.
Fixing Impedance-Induced Noise: Ranked by Cost and Effectiveness
Once you have calculated $Z_{in}$ and identified a mismatch or a noise-vulnerable node, you need a fix. Here is the definitive list of impedance corrections, ranked from cheapest to most complex.
- Series Source Termination (Cost: ~$0.01 | Effectiveness: High for digital lines): Place a resistor (typically 22Ω to 33Ω) in series with the driver, right at the source pin. This matches the low output impedance of the driver to the characteristic impedance of the PCB trace (usually 50Ω), absorbing reflections before they bounce back. This is the absolute best fix for ringing on microcontroller GPIO lines driving long traces.
- Parallel End Termination (Cost: ~$0.01 | Effectiveness: High for RF/Coax): Place a 50Ω resistor to ground at the receiving end of a transmission line. This prevents reflections but draws continuous DC current. Use this for high-speed clock lines or coaxial cables, but avoid it on battery-powered low-frequency analog sensors.
- RC Snubber Networks (Cost: ~$0.05 | Effectiveness: High for inductive kickback): If your calculated $Z_{in}$ is interacting with parasitic trace inductance to create high-frequency ringing, an RC snubber (e.g., 100Ω in series with 1nF) placed across the node provides a low-impedance path for the high-frequency noise while blocking DC.
- Active Buffering (Cost: $0.50 - $2.00 | Effectiveness: Maximum for analog): If you must drive a low-impedance load (like a 50Ω ADC input) from a high-impedance source (like a 100kΩ voltage divider), insert a unity-gain op-amp buffer. This transforms the impedance, presenting a high $Z_{in}$ to the source and a low $Z_{out}$ to the load.
- Guard Rings / Driven Shields (Cost: PCB Fab Premium | Effectiveness: High for picoamp circuits): For electrometer-level circuits where $Z_{in} > 10^{12}\Omega$, PCB surface leakage becomes a conductive noise path. Surrounding the input trace with a guard ring driven at the exact same potential as the input eliminates the voltage gradient, reducing leakage current to zero.
Note on Shielding: If your impedance calculation reveals susceptibility to radiated EMI and you opt for a shielded cable, you must terminate the shield correctly. A 'pigtail' ground wire creates an inductor that ruins the shield's high-frequency effectiveness. Always use a 360-degree backshell or direct PCB chassis-ground via stitching to maintain continuous impedance along the shield path.
Before and After: Proving the Fix with a Meter or Scope
You cannot manage what you do not measure. According to the Keysight Impedance Measurement Handbook, dynamic impedance changes with frequency, meaning a static DC multimeter reading is useless for signal integrity. Here is the before-and-after measurement method to prove your fix using standard bench equipment.
Step 1: The Voltage Divider Method (Measuring $Z_{in}$ with a Scope)
To prove your calculated $Z_{in}$ matches reality, use your oscilloscope and a function generator.
- Connect your function generator to the circuit input via a known, precise series resistor ($R_s$). Choose an $R_s$ close to your calculated $Z_{in}$ (e.g., if you calculated 10kΩ, use a 10kΩ 1% metal film resistor).
- Measure the open-circuit voltage of the function generator ($V_{source}$) with your scope probe directly at the generator output.
- Connect the probe to the actual input node of your circuit ($V_{in}$) while the generator is driving the signal through $R_s$.
- Calculate the actual impedance using the rearranged voltage divider formula: $Z_{in} = R_s \times [V_{in} / (V_{source} - V_{in})]$.
If your calculated $Z_{in}$ was 10kΩ, and your $V_{source}$ is 2.0Vpp, you should measure exactly 1.0Vpp at the input node. If you measure 1.4Vpp, your actual $Z_{in}$ is higher than calculated, likely due to parasitic PCB capacitance or component tolerances.
Step 2: Before and After Ringing Measurement
If your issue is signal integrity (reflections due to impedance mismatch), you must look at the time-domain edges.
- Before the Fix: Probe the receiving end of a 50Ω trace driven by a 3.3V microcontroller GPIO with a fast edge rate (<5ns). You will likely see the signal overshoot to 4.5V, ring down to 2.0V, and oscillate before settling. This is a classic impedance mismatch where the low $Z_{out}$ of the GPIO hits the high $Z_{in}$ of the receiver.
- Apply the Fix: Solder a 33Ω series resistor at the GPIO pin (Source Termination).
- After the Fix: Probe the receiver again. The overshoot will vanish. The signal will rise smoothly to 3.3V with a slightly rounded edge (due to the RC filter formed by the 33Ω resistor and the receiver's parasitic capacitance). The reflections are absorbed.
For advanced verification on high-speed RF boards, a Time Domain Reflectometer (TDR) or a scope with TDR capabilities will send a fast edge down the trace and plot impedance versus distance, allowing you to pinpoint exactly where a via or connector is breaking your 50Ω target. As detailed in All About Circuits' guide to impedance, mastering these measurements transitions you from guessing component values to engineering predictable, noise-immune systems.
