A boolean truth table maps discrete input states to output states for digital logic gates. In pure mathematics, a 1 or 0 is an abstract concept. On the workbench, a 1 or 0 is a specific voltage threshold dictated by the physical silicon family you are wiring. Whether you are debugging a custom PCB, interfacing a 5V sensor to a 3.3V ESP32, or building a discrete logic clock divider, the truth table is your baseline schematic for expected behavior.

Below is the definitive hardware reference for standard 2-input logic gates, followed by the voltage thresholds and timing derating factors that determine if your circuit will actually work in physical reality.

Standard 2-Input Boolean Truth Tables

The following master table consolidates the output states for the five primary 2-input logic gates. This reference aligns with the standard logic symbols and definitions established in IEEE/ANSI Std 91-1984 and standard digital electronics curricula. Bookmark this section for quick bench lookups.

Master 2-Input Boolean Truth Table (Positive Logic)
Input A Input B AND (74x08) NAND (74x00) OR (74x32) NOR (74x02) XOR (74x86) XNOR (74x266)
0 (Low) 0 (Low) 0 1 0 1 0 1
0 (Low) 1 (High) 0 1 1 0 1 0
1 (High) 0 (Low) 0 1 1 0 1 0
1 (High) 1 (High) 1 0 1 0 0 1
How to read this table: The 0 and 1 designations represent logical Low and High states, respectively. For a standard 5V 74HC series IC, a "0" corresponds to an input voltage near 0V (GND), and a "1" corresponds to an input voltage near 5V (VCC). The part numbers in parentheses (e.g., 74x08) denote the standard DIP IC package containing four of these specific gates, where "x" represents the logic family (LS for TTL, HC for CMOS).

Voltage Thresholds: Which Column Applies to Your Installation?

A truth table tells you what the gate will do, but the datasheet tells you how it recognizes the inputs. The most common point of failure in discrete logic design is assuming a "1" is universally 5V. When interfacing different logic families or voltage domains, you must consult the voltage threshold table to see which column applies to your specific installation.

According to Texas Instruments logic design guidelines, you must ensure the output high voltage ($V_{OH}$) of the driving gate exceeds the input high threshold ($V_{IH}$) of the receiving gate, with adequate noise margin.

Logic Family Voltage Thresholds and Noise Margins
Logic Family (VCC) $V_{IL}$ (Max Low Input) $V_{IH}$ (Min High Input) $V_{OL}$ (Max Low Output) $V_{OH}$ (Min High Output) Worst-Case Noise Margin
74LS (TTL, 5V) 0.8V 2.0V 0.4V 2.7V 0.7V
74HC (CMOS, 5V) 1.5V 3.5V 0.1V 4.9V 1.4V
CD4000 (CMOS, 10V) 3.0V 7.0V 0.5V 9.5V 2.5V
LVCMOS (3.3V) 0.8V 2.0V 0.4V 2.9V 0.9V

Which column applies to you? If you are reading the output of a sensor, look at the $V_{IH}$ and $V_{IL}$ columns to verify your microcontroller will register the signal. If you are driving a relay module or another IC, look at the $V_{OH}$ and $V_{OL}$ columns to ensure your gate can source or sink enough voltage to trigger the next stage.

Interfacing Warning: Never directly drive a 5V 74HC CMOS input with a 5V 74LS TTL output without a pull-up resistor. The 74LS $V_{OH}$ (2.7V) falls dangerously below the 74HC $V_{IH}$ (3.5V), placing the CMOS gate in its linear region, causing excessive current draw and potential thermal failure.

What the Truth Table Cannot Tell You: Timing and Derating

A boolean truth table represents an idealized, zero-time universe. It cannot tell you about propagation delay, setup/hold times, or capacitive loading. In physical hardware, these factors dictate whether your logic circuit functions correctly at speed or devolves into a glitching mess.

Propagation Delay and Capacitive Derating

Just as ambient temperature derates the ampacity of a copper wire, capacitive loading derates the propagation delay ($t_{pd}$) of a logic gate. Every logic gate input presents a small parasitic capacitance (typically 3pF to 10pF). When you wire one gate output to multiple inputs (fan-out), or run long PCB traces, you increase the total load capacitance ($C_L$).

Consider the 74HC08 (Quad 2-Input AND Gate) operating at 5V:

  • Base Value: At $C_L$ = 15pF, typical $t_{pd}$ is 9 ns.
  • Derated Value: At $C_L$ = 50pF (e.g., driving 5 standard HC inputs plus trace capacitance), $t_{pd}$ derates to approximately 18 ns.

If you are designing a high-speed clock divider running at 50 MHz (20 ns period), a derated 18 ns propagation delay consumes nearly your entire timing budget, leaving almost zero margin for setup and hold times. The truth table shows the correct logical state, but the oscilloscope will show the output arriving too late to be clocked properly by the next flip-flop.

Timing Hazards and Metastability

Truth tables assume inputs change instantaneously and simultaneously. In reality, signals travel through different path lengths. If an XOR gate receives a changing signal on Input A directly, but Input B receives the same signal delayed by an inverter (NOT gate), there is a brief window where both inputs are simultaneously High or Low due to the inverter's propagation delay.

This creates a glitch (a momentary false output spike) that the truth table does not predict. In combinatorial logic, this might just cause a brief LED flicker. In sequential logic (feeding a clock or latch), this glitch can trigger a false state change, leading to system lockups. To prevent this, hardware designers use synchronous design practices, routing all signals through a master clock and utilizing D-flip-flops to mask combinatorial glitches.

Bench Troubleshooting Rule: If your logic circuit outputs the wrong state intermittently, but static multimeter tests match the truth table, you are likely suffering from a timing hazard or a floating input. Always tie unused CMOS inputs to VCC or GND; leaving them floating allows ambient EMI to toggle the gate, causing erratic outputs and massive VCC current spikes.