A boolean truth table maps every possible combination of binary inputs to a deterministic binary output for a digital logic gate. Governed by the symbolic standards of IEEE Std 91/91a and IEC 60617-12, these tables are the absolute foundation of digital circuit design. However, a textbook table only tells half the story. On the bench, you must account for active-low assertions, propagation delays, and logic family voltage thresholds. Below is the definitive reference chart, followed by the hardware realities that dictate which specific integrated circuit (IC) you should actually solder to your board.
The Master Boolean Truth Table (IEEE/IEC Standard)
How to read this table: This chart assumes standard 2-input positive logic (Active-High). Input A and Input B represent the voltage states at the physical pins (0 = Low/GND, 1 = High/VCC). Output Y (Active-High) shows the standard boolean result. Output Y (Active-Low) shows the inverted result, which applies when you are using NAND/NOR gates or dealing with inverted chip-select lines. If your microcontroller GPIO is configured with an internal pull-up resistor and switches to ground, you must read from the Active-Low column to predict the physical behavior.
| Gate Type | IEEE/IEC Symbol | Input A | Input B | Output Y (Active-High) | Output Y (Active-Low / Inverted) |
|---|---|---|---|---|---|
| AND | & / DShape | 0 | 0 | 0 | 1 |
| AND | & / DShape | 0 | 1 | 0 | 1 |
| AND | & / DShape | 1 | 0 | 0 | 1 |
| AND | & / DShape | 1 | 1 | 1 | 0 |
| OR | ≥1 / Curved | 0 | 0 | 0 | 1 |
| OR | ≥1 / Curved | 0 | 1 | 1 | 0 |
| OR | ≥1 / Curved | 1 | 0 | 1 | 0 |
| OR | ≥1 / Curved | 1 | 1 | 1 | 0 |
| XOR | =1 / Curved+ | 0 | 0 | 0 | 1 |
| XOR | =1 / Curved+ | 0 | 1 | 1 | 0 |
| XOR | =1 / Curved+ | 1 | 0 | 1 | 0 |
| XOR | =1 / Curved+ | 1 | 1 | 0 | 1 |
| NAND | & + Bubble | 0 | 0 | 1 | 0 |
| NAND | & + Bubble | 0 | 1 | 1 | 0 |
| NAND | & + Bubble | 1 | 0 | 1 | 0 |
| NAND | & + Bubble | 1 | 1 | 0 | 1 |
| NOR | ≥1 + Bubble | 0 | 0 | 1 | 0 |
| NOR | ≥1 + Bubble | 0 | 1 | 0 | 1 |
| NOR | ≥1 + Bubble | 1 | 0 | 0 | 1 |
| NOR | ≥1 + Bubble | 1 | 1 | 0 | 1 |
Quick-Jump Rows: The Most Queried Logic States
When debugging a stalled state machine or a faulty interlock circuit, these are the specific rows where designers make assumptions that fail on the bench:
- XOR (1, 1 → 0): Often mistakenly assumed to output 1. XOR is an "inequality" detector. If both inputs are HIGH, the output is LOW. Use XNOR if you need an "equality" detector.
- NAND (0, 0 → 1): The universal gate. Notice that if any input is 0, the output is 1. This makes NAND gates ideal for active-low reset circuits where pulling any single line low triggers the reset.
- OR (0, 0 → 0): The only state where an OR gate outputs LOW. In safety interlocks wired with normally-open switches, this is your "all clear" state.
Active-Low, Inverted Inputs, and "Derating" Your Logic
In wire sizing, "derating" reduces ampacity based on ambient temperature. In digital logic, you must "derate" your expected truth table outputs when dealing with inverted inputs (bubbles) and active-low chip selects ($\overline{CS}$, $\overline{OE}$, $\overline{WE}$).
How inverted inputs modify the base value: If you are using an AND gate, but Input A has an inversion bubble (often seen in multiplexers or flip-flops), the physical pin requires a LOW (0) to satisfy the internal "1" requirement of the AND function. Therefore, to get a HIGH output, your physical truth table row shifts: you must apply A=0, B=1.
Which column applies to your installation? If you are interfacing with an ESP32 or Arduino where GPIO pins default to HIGH via pull-up resistors and are triggered by pulling to GND (like a button press), your "asserted" state is 0. You must evaluate your circuit using the Active-Low column of the master table above to predict the physical behavior of the downstream logic.
What the Truth Table Cannot Tell You (Hardware Reality)
A boolean truth table assumes ideal, instantaneous mathematics. Physical silicon introduces constraints that will break your circuit if ignored. Here is what the table hides:
1. Propagation Delay ($t_{pd}$)
The output does not change the exact nanosecond the input changes. A standard 74HC08 AND gate has a typical $t_{pd}$ of 15ns at 5V. If you cascade five gates in a ripple-carry adder, you accumulate 75ns of delay. In high-speed SPI or I2C bus steering, this delay can violate setup and hold times, causing metastability.
2. Floating CMOS Inputs
The truth table assumes inputs are firmly at 0 or 1. If you leave an input pin floating on a 4000-series CMOS chip (like a CD4011), the input impedance is so high that ambient electromagnetic noise will cause the internal transistors to rapidly switch back and forth. This results in massive $I_{DD}$ current draw, overheating the IC, and unpredictable outputs. Always tie unused CMOS inputs to VCC or GND.
3. Fan-Out and Logic Family Mismatches
The table assumes an output can drive infinite inputs. In reality, a 74LS00 (TTL) output HIGH voltage ($V_{OH}$) is only about 2.7V. A 74HC00 (CMOS) input requires a HIGH voltage ($V_{IH}$) of at least 3.5V when running at 5V. If you use the truth table to design a circuit where an LS chip drives an HC chip, the HC chip will read the LS "HIGH" as a "LOW" or float into an undefined state.
Decision Tree: Picking the Right Logic IC for Your Build
Stop guessing which logic family to buy. Use this decision path to terminate on the exact part number for your next PCB or breadboard prototype.
| If Your System Requirement Is... | Then Choose This Logic Family | Concrete Part Number (Quad 2-Input AND) |
|---|---|---|
| 5V supply, interfacing with standard Arduino Uno/Mega, moderate speed (up to 20MHz). | 74HC (High-Speed CMOS). Best all-rounder, low power, 5V tolerant. | SN74HC08N (TI) or MC74HC08ANG (onsemi) |
| 3.3V supply, interfacing directly with ESP32, STM32, or Raspberry Pi Pico GPIOs. | 74LVC (Low-Voltage CMOS). Specifically designed for 3.3V logic thresholds. | SN74LVC08APWR (TI) or 74LVC08APW (Nexperia) |
| Wide voltage range (3V to 15V), battery-powered, very low speed (audio or slow timing). | 4000B (Buffered CMOS). Wide VCC tolerance, but slow and fragile to static. | CD4081BE (TI) or HEF4081BT (Nexperia) |
| 5V supply, but you need to drive high-current loads (relays, LEDs) directly from the gate. | 74ACT (Advanced CMOS with TTL levels) or use an open-collector driver. | SN74ACT08N (TI) + ULN2003A Darlington array for heavy loads. |
Final Verdict: For 90% of modern hobbyist and prototyping builds operating at 3.3V or 5V, the 74LVC series is the definitive choice. It natively supports 3.3V logic levels while many LVC chips are actually 5V-tolerant on their inputs, bridging the gap between legacy 5V sensors and modern 3.3V microcontrollers without requiring external level shifters.
