A boolean table (commonly called a truth table) is the foundational lookup matrix for digital electronics, mapping discrete input states to a definitive output state. But on the workbench, a 1 or 0 is never just a mathematical abstraction—it is a specific physical voltage governed by the IC family you are using. If you are wiring a 74LS08 AND gate alongside a 74HC00 NAND gate, relying on an abstract boolean table without checking the electrical thresholds will result in floating inputs, excessive heat, and erratic logic states.
This reference provides the standardized boolean logic mappings alongside the critical electrical voltage thresholds defined by the Texas Instruments Logic Data Book and ANSI/IEEE Std 91-1984, giving you the exact numbers needed to design reliable digital circuits.
How to Read a Practical Boolean Table
Before wiring your breadboard or designing your PCB, you must understand how to read the columns in a practical, hardware-level boolean table. A purely mathematical table only shows 1s and 0s. An engineering reference table adds the physical voltage boundaries.
Which column applies to your installation?
Look at your IC's part number. If it starts with 74LS or 74F, use the TTL columns. These older bipolar junction transistor (BJT) based chips have asymmetrical voltage thresholds and draw continuous current. If your IC starts with 74HC, 74HCT, or 4000, use the CMOS columns. CMOS chips use MOSFETs, draw near-zero static current, and have symmetrical, rail-to-rail voltage thresholds.
- $V_{IL}$ (Max Low Input): The highest voltage the IC will still guarantee it reads as a logical '0'. Anything above this enters the undefined zone.
- $V_{IH}$ (Min High Input): The lowest voltage the IC will guarantee it reads as a logical '1'.
- Undefined Zone: The voltage gap between $V_{IL}$ and $V_{IH}$. Never leave an input pin in this range; it causes internal shoot-through current and oscillation.
Master Boolean & Voltage Threshold Reference
The following table combines the standard 2-input boolean logic mappings (per All About Circuits Digital Logic standards) with the physical voltage requirements for the two most common 5V logic families on the market.
| Gate Type (IC Example) | Input A | Input B | Output Y (Logic) | 74LS TTL $V_{IL}$ / $V_{IH}$ | 74HC CMOS $V_{IL}$ / $V_{IH}$ |
|---|---|---|---|---|---|
| AND (74LS08 / 74HC08) | 0 | 0 | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| AND | 0 | 1 | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| AND | 1 | 0 | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| AND | 1 | 1 | 1 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| NAND (74LS00 / 74HC00) | 1 | 1 | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| NAND | Any other combination | - | 1 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| OR (74LS32 / 74HC32) | 0 | 0 | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| OR | Any '1' present | - | 1 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| XOR (74LS86 / 74HC86) | 0 / 1 or 1 / 0 | - | 1 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
| XOR | Same (0,0 or 1,1) | - | 0 | 0.8V max / 2.0V min | 1.5V max / 3.15V min |
How derating rows modify the base value:
The values above are baseline. If your circuit operates at 85°C (common in automotive or enclosed industrial panels), the $V_{IH}$ minimum drops by approximately 0.1V to 0.2V depending on the silicon process, shrinking your noise margin. Furthermore, if you are driving a heavy fan-out (e.g., one 74HC output driving 10 TTL inputs), the output high voltage ($V_{OH}$) will sag due to internal resistance. You must derate your expected output voltage by roughly 0.05V per milliamp of sourced current. Always ensure your sagging $V_{OH}$ remains strictly above the receiving IC's $V_{IH}$ threshold.
What the Boolean Table Cannot Tell You
A boolean table is a static, steady-state map. It is blind to the physical realities of electrons moving through silicon. When debugging a circuit that 'should work according to the truth table,' check these three missing variables:
- Propagation Delay ($t_{pd}$): The boolean table implies instant state changes. In reality, a 74HC00 NAND gate takes about 8ns to flip its output after the inputs change. If you cascade 20 gates in series, you accumulate 160ns of delay, which can cause timing violations in high-speed clocked circuits.
- Metastability: If an input signal transitions from 0 to 1 at the exact moment a flip-flop is clocked, the output may enter a metastable state—hovering in the undefined voltage zone for nanoseconds or microseconds before snapping to a 1 or 0. The boolean table has no symbol for this failure mode.
- Shoot-Through Current: During the brief nanosecond an output transitions from 0 to 1, both the internal pull-up and pull-down MOSFETs are partially ON simultaneously. This creates a momentary short circuit from VCC to GND. While the boolean table shows a clean transition, your oscilloscope will show a sharp current spike on the power rail, which necessitates 100nF decoupling capacitors on every IC VCC pin.
Boolean Table Lookup FAQ
How do I map a boolean table when mixing 5V TTL and 3.3V CMOS logic?
When a 3.3V microcontroller (like an ESP32) drives a 5V 74HCT logic gate, the boolean table mapping still holds because the 74HCT family is specifically designed with TTL-compatible input thresholds. The 3.3V high output ($V_{OH}$) of the ESP32 is well above the 2.0V $V_{IH}$ requirement of the 74HCT gate. However, if you are driving a standard 74HC gate, the 3.3V signal will fail to cross the 3.15V $V_{IH}$ threshold, resulting in a permanent logical '0' or an oscillating state. Use a dedicated level shifter (like the TXB0104) or stick to 74HCT ICs for 3.3V-to-5V translation.
Why does my boolean table show an 'X' (Don't Care) and how do I wire it?
In Karnaugh maps and advanced boolean tables, an 'X' denotes a 'Don't Care' condition—an input combination that will never occur in normal operation, or where the output state is irrelevant to the system. Physically, never leave a 'Don't Care' input pin unconnected (floating) on a CMOS IC. A floating pin acts as an antenna, picking up EMI and causing the internal MOSFETs to rapidly switch, destroying the chip via thermal runaway. Always tie 'Don't Care' inputs to VCC via a 10kΩ pull-up resistor or directly to GND, depending on which simplifies your PCB routing.
How do temperature derating rows modify the base boolean table voltages?
Silicon conductivity changes with heat. As ambient temperature rises from the standard 25°C to the industrial maximum of 85°C or 125°C, the threshold voltages shift. For standard 74HC CMOS, the $V_{IH}$ (minimum high voltage) actually decreases slightly, which seems beneficial, but the $V_{IL}$ (maximum low voltage) increases. This shrinks your noise margin—the protective voltage buffer between your signal and the undefined zone. If you are designing for high-temperature environments, assume your noise margin is reduced by 15% to 20% compared to the datasheet's 25°C spec sheet, and keep signal traces short to minimize inductive ringing.
